[AVX512] Enabling bit logic lowering

[oota-llvm.git] / test / CodeGen / X86 / avx-cvt.ll

diff --git a/test/CodeGen/X86/avx-cvt.ll b/test/CodeGen/X86/avx-cvt.ll
index 5fe207e06000f596f4b691ac152a59d8eeae7922..22fad7ce4b7d98a6a8f2315ab3c000ca7ff26acc 100644 (file)
--- a/test/CodeGen/X86/avx-cvt.ll
+++ b/test/CodeGen/X86/avx-cvt.ll
@@ -6,17 +6,28 @@ define <8 x float> @sitofp00(<8 x i32> %a) nounwind {
   ret <8 x float> %b
 }
 
-; CHECK: vcvtdq2ps
-; CHECK-NEXT: vcvtps2pd
+; CHECK: vcvttps2dq %ymm
+define <8 x i32> @fptosi00(<8 x float> %a) nounwind {
+  %b = fptosi <8 x float> %a to <8 x i32>
+  ret <8 x i32> %b
+}
+
+; CHECK: vcvtdq2pd %xmm
 define <4 x double> @sitofp01(<4 x i32> %a) {
   %b = sitofp <4 x i32> %a to <4 x double>
   ret <4 x double> %b
 }
 
-; CHECK: vcvttps2dq %ymm
-define <8 x i32> @fptosi00(<8 x float> %a) nounwind {
-  %b = fptosi <8 x float> %a to <8 x i32>
-  ret <8 x i32> %b
+; CHECK: vcvtdq2ps %ymm
+define <8 x float> @sitofp02(<8 x i16> %a) {
+  %b = sitofp <8 x i16> %a to <8 x float>
+  ret <8 x float> %b
+}
+
+; CHECK: vcvttpd2dqy %ymm
+define <4 x i32> @fptosi01(<4 x double> %a) {
+  %b = fptosi <4 x double> %a to <4 x i32>
+  ret <4 x i32> %b
 }
 
 ; CHECK: vcvtpd2psy %ymm
@@ -41,7 +52,7 @@ entry:
   ret double %conv
 }
 
-; CHECK: vcvtsi2sd (%
+; CHECK: vcvtsi2sdl (%
 define double @funcB(i32* nocapture %e) nounwind uwtable readonly ssp {
 entry:
   %tmp1 = load i32* %e, align 4
@@ -49,7 +60,7 @@ entry:
   ret double %conv
 }
 
-; CHECK: vcvtsi2ss (%
+; CHECK: vcvtsi2ssl (%
 define float @funcC(i32* nocapture %e) nounwind uwtable readonly ssp {
 entry:
   %tmp1 = load i32* %e, align 4