ret <4 x i64> %shuffle
}
-; CHECK: movlhps
+; CHECK: vpunpcklqdq
; CHECK-NEXT: vextractf128 $1
-; CHECK-NEXT: movlhps
+; CHECK-NEXT: vpunpcklqdq
; CHECK-NEXT: vinsertf128 $1
define <4 x i64> @C(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
entry:
}
; CHECK: vpshufd $-96
-; CHECK: vpshufd $-6
+; CHECK: vpunpckhdq
; CHECK: vinsertf128 $1
define <8 x i32> @D(<8 x i32> %a, <8 x i32> %b) nounwind uwtable readnone ssp {
entry:
%res = insertelement <16 x i16> <i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 %a, i32 0
ret <16 x i16> %res
}
+
+;;; Check that VMOVPQIto64rr generates the assembly string "vmovq". Previously
+;;; an incorrect mnemonic of "movd" was printed for this instruction.
+; CHECK: VMOVPQIto64rr
+; CHECK: vmovq
+define i64 @VMOVPQIto64rr(<2 x i64> %a) {
+entry:
+ %vecext.i = extractelement <2 x i64> %a, i32 0
+ ret i64 %vecext.i
+}