-; RUN: llc < %s -mtriple=x86_64-apple-darwin -disable-fp-elim | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -disable-fp-elim | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim | FileCheck --check-prefix=SSE %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -disable-fp-elim | FileCheck --check-prefix=AVX %s
+
; Stackmap Header: no constants - 6 callsites
-; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
-; CHECK-NEXT: __LLVM_StackMaps:
+; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
+; CHECK-NEXT: __LLVM_StackMaps:
; Header
-; CHECK-NEXT: .long 0
+; CHECK-NEXT: .byte 1
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 0
+; Num Functions
+; CHECK-NEXT: .long 8
; Num Constants
-; CHECK-NEXT: .long 0
+; CHECK-NEXT: .long 0
; Num Callsites
-; CHECK-NEXT: .long 8
+; CHECK-NEXT: .long 8
+; Functions and stack size
+; CHECK-NEXT: .quad _test
+; CHECK-NEXT: .quad 8
+; CHECK-NEXT: .quad _property_access1
+; CHECK-NEXT: .quad 8
+; CHECK-NEXT: .quad _property_access2
+; CHECK-NEXT: .quad 24
+; CHECK-NEXT: .quad _property_access3
+; CHECK-NEXT: .quad 24
+; CHECK-NEXT: .quad _anyreg_test1
+; CHECK-NEXT: .quad 56
+; CHECK-NEXT: .quad _anyreg_test2
+; CHECK-NEXT: .quad 56
+; CHECK-NEXT: .quad _patchpoint_spilldef
+; CHECK-NEXT: .quad 56
+; CHECK-NEXT: .quad _patchpoint_spillargs
+; CHECK-NEXT: .quad 88
+
+; No constants
+
+; Callsites
; test
; CHECK-LABEL: .long L{{.*}}-_test
; CHECK-NEXT: .short 0
ret i64 %result
}
+; Make sure all regs are spilled
+define anyregcc void @anyregcc1() {
+entry:
+;SSE-LABEL: anyregcc1
+;SSE: pushq %rbp
+;SSE: pushq %rax
+;SSE: pushq %r15
+;SSE: pushq %r14
+;SSE: pushq %r13
+;SSE: pushq %r12
+;SSE: pushq %r11
+;SSE: pushq %r10
+;SSE: pushq %r9
+;SSE: pushq %r8
+;SSE: pushq %rdi
+;SSE: pushq %rsi
+;SSE: pushq %rdx
+;SSE: pushq %rcx
+;SSE: pushq %rbx
+;SSE: movaps %xmm15
+;SSE-NEXT: movaps %xmm14
+;SSE-NEXT: movaps %xmm13
+;SSE-NEXT: movaps %xmm12
+;SSE-NEXT: movaps %xmm11
+;SSE-NEXT: movaps %xmm10
+;SSE-NEXT: movaps %xmm9
+;SSE-NEXT: movaps %xmm8
+;SSE-NEXT: movaps %xmm7
+;SSE-NEXT: movaps %xmm6
+;SSE-NEXT: movaps %xmm5
+;SSE-NEXT: movaps %xmm4
+;SSE-NEXT: movaps %xmm3
+;SSE-NEXT: movaps %xmm2
+;SSE-NEXT: movaps %xmm1
+;SSE-NEXT: movaps %xmm0
+;AVX-LABEL:anyregcc1
+;AVX: pushq %rbp
+;AVX: pushq %rax
+;AVX: pushq %r15
+;AVX: pushq %r14
+;AVX: pushq %r13
+;AVX: pushq %r12
+;AVX: pushq %r11
+;AVX: pushq %r10
+;AVX: pushq %r9
+;AVX: pushq %r8
+;AVX: pushq %rdi
+;AVX: pushq %rsi
+;AVX: pushq %rdx
+;AVX: pushq %rcx
+;AVX: pushq %rbx
+;AVX: vmovaps %ymm15
+;AVX-NEXT: vmovaps %ymm14
+;AVX-NEXT: vmovaps %ymm13
+;AVX-NEXT: vmovaps %ymm12
+;AVX-NEXT: vmovaps %ymm11
+;AVX-NEXT: vmovaps %ymm10
+;AVX-NEXT: vmovaps %ymm9
+;AVX-NEXT: vmovaps %ymm8
+;AVX-NEXT: vmovaps %ymm7
+;AVX-NEXT: vmovaps %ymm6
+;AVX-NEXT: vmovaps %ymm5
+;AVX-NEXT: vmovaps %ymm4
+;AVX-NEXT: vmovaps %ymm3
+;AVX-NEXT: vmovaps %ymm2
+;AVX-NEXT: vmovaps %ymm1
+;AVX-NEXT: vmovaps %ymm0
+ call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{rbp},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15}"()
+ ret void
+}
+
+; Make sure we don't spill any XMMs/YMMs
+declare anyregcc void @foo()
+define void @anyregcc2() {
+entry:
+;SSE-LABEL: anyregcc2
+;SSE-NOT: movaps %xmm
+;AVX-LABEL: anyregcc2
+;AVX-NOT: vmovups %ymm
+ %a0 = call <2 x double> asm sideeffect "", "={xmm0}"() nounwind
+ %a1 = call <2 x double> asm sideeffect "", "={xmm1}"() nounwind
+ %a2 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
+ %a3 = call <2 x double> asm sideeffect "", "={xmm3}"() nounwind
+ %a4 = call <2 x double> asm sideeffect "", "={xmm4}"() nounwind
+ %a5 = call <2 x double> asm sideeffect "", "={xmm5}"() nounwind
+ %a6 = call <2 x double> asm sideeffect "", "={xmm6}"() nounwind
+ %a7 = call <2 x double> asm sideeffect "", "={xmm7}"() nounwind
+ %a8 = call <2 x double> asm sideeffect "", "={xmm8}"() nounwind
+ %a9 = call <2 x double> asm sideeffect "", "={xmm9}"() nounwind
+ %a10 = call <2 x double> asm sideeffect "", "={xmm10}"() nounwind
+ %a11 = call <2 x double> asm sideeffect "", "={xmm11}"() nounwind
+ %a12 = call <2 x double> asm sideeffect "", "={xmm12}"() nounwind
+ %a13 = call <2 x double> asm sideeffect "", "={xmm13}"() nounwind
+ %a14 = call <2 x double> asm sideeffect "", "={xmm14}"() nounwind
+ %a15 = call <2 x double> asm sideeffect "", "={xmm15}"() nounwind
+ call anyregcc void @foo()
+ call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},{xmm8},{xmm9},{xmm10},{xmm11},{xmm12},{xmm13},{xmm14},{xmm15}"(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3, <2 x double> %a4, <2 x double> %a5, <2 x double> %a6, <2 x double> %a7, <2 x double> %a8, <2 x double> %a9, <2 x double> %a10, <2 x double> %a11, <2 x double> %a12, <2 x double> %a13, <2 x double> %a14, <2 x double> %a15)
+ ret void
+}
+
declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)