Instruction scheduling itinerary for Intel Atom.

[oota-llvm.git] / test / CodeGen / X86 / add.ll

diff --git a/test/CodeGen/X86/add.ll b/test/CodeGen/X86/add.ll
index 62c898025c80adacdd62b9e2c9b1d262970217e7..8e871f4aeb4df802f34f9c7118266c47ee66ff31 100644 (file)
--- a/test/CodeGen/X86/add.ll
+++ b/test/CodeGen/X86/add.ll
@@ -1,6 +1,8 @@
-; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32
-; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64
-; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mcpu=generic -march=x86 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux -join-physregs | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-win32 -join-physregs | FileCheck %s -check-prefix=X64
+
+; Some of these tests depend on -join-physregs to commute instructions.
 
 ; The immediate can be encoded in a smaller way if the
 ; instruction is a sub instead of an add.
@@ -133,3 +135,18 @@ define i32 @test9(i32 %x, i32 %y) nounwind readnone {
 ; X64: subl
 ; X64: ret
 }
+
+define i1 @test10(i32 %x) nounwind {
+entry:
+  %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %x, i32 1)
+  %obit = extractvalue {i32, i1} %t, 1
+  ret i1 %obit
+
+; X32: test10:
+; X32: incl
+; X32-NEXT: seto
+
+; X64: test10:
+; X64: incl
+; X64-NEXT: seto
+}