; RUN: llc -march=x86-64 -mcpu=corei7 -mattr=+avx < %s | FileCheck %s
+; RUN: llc -march=x86-64 -mcpu=corei7 -mattr=+avx -addr-sink-using-gep=1 < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.8.0"
ret void
}
+; No vectors because we use noimplicitfloat
+; CHECK: merge_const_store_no_vec
+; CHECK-NOT: vmovups
+; CHECK: ret
+define void @merge_const_store_no_vec(i32 %count, %struct.B* nocapture %p) noimplicitfloat{
+ %1 = icmp sgt i32 %count, 0
+ br i1 %1, label %.lr.ph, label %._crit_edge
+.lr.ph:
+ %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
+ %.01 = phi %struct.B* [ %11, %.lr.ph ], [ %p, %0 ]
+ %2 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0
+ store i32 0, i32* %2, align 4
+ %3 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1
+ store i32 0, i32* %3, align 4
+ %4 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2
+ store i32 0, i32* %4, align 4
+ %5 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3
+ store i32 0, i32* %5, align 4
+ %6 = getelementptr inbounds %struct.B* %.01, i64 0, i32 4
+ store i32 0, i32* %6, align 4
+ %7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 5
+ store i32 0, i32* %7, align 4
+ %8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 6
+ store i32 0, i32* %8, align 4
+ %9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 7
+ store i32 0, i32* %9, align 4
+ %10 = add nsw i32 %i.02, 1
+ %11 = getelementptr inbounds %struct.B* %.01, i64 1
+ %exitcond = icmp eq i32 %10, %count
+ br i1 %exitcond, label %._crit_edge, label %.lr.ph
+._crit_edge:
+ ret void
+}
+
; Move the constants using a single vector store.
; CHECK: merge_const_store_vec
-; CHECK: vmovups %ymm0, (%rsi)
+; CHECK: vmovups
; CHECK: ret
define void @merge_const_store_vec(i32 %count, %struct.B* nocapture %p) nounwind uwtable noinline ssp {
%1 = icmp sgt i32 %count, 0
}
-;CHECK: merge_loads_i16
+;CHECK-LABEL: merge_loads_i16:
; load:
;CHECK: movw
; store:
}
; The loads and the stores are interleved. Can't merge them.
-;CHECK: no_merge_loads
+;CHECK-LABEL: no_merge_loads:
;CHECK: movb
;CHECK: movb
;CHECK: movb
}
-;CHECK: merge_loads_integer
+;CHECK-LABEL: merge_loads_integer:
; load:
;CHECK: movq
; store:
}
-;CHECK: merge_loads_vector
+;CHECK-LABEL: merge_loads_vector:
; load:
;CHECK: movups
; store:
ret void
}
-;CHECK: merge_loads_no_align
+;CHECK-LABEL: merge_loads_no_align:
; load:
;CHECK: movl
;CHECK: movl
ret void
}
+; Make sure that we merge the consecutive load/store sequence below and use a
+; word (16 bit) instead of a byte copy.
+; CHECK: MergeLoadStoreBaseIndexOffset
+; CHECK: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]]
+; CHECK: movw [[REG]], (%{{.*}})
+define void @MergeLoadStoreBaseIndexOffset(i64* %a, i8* %b, i8* %c, i32 %n) {
+ br label %1
+
+; <label>:1
+ %.09 = phi i32 [ %n, %0 ], [ %11, %1 ]
+ %.08 = phi i8* [ %b, %0 ], [ %10, %1 ]
+ %.0 = phi i64* [ %a, %0 ], [ %2, %1 ]
+ %2 = getelementptr inbounds i64* %.0, i64 1
+ %3 = load i64* %.0, align 1
+ %4 = getelementptr inbounds i8* %c, i64 %3
+ %5 = load i8* %4, align 1
+ %6 = add i64 %3, 1
+ %7 = getelementptr inbounds i8* %c, i64 %6
+ %8 = load i8* %7, align 1
+ store i8 %5, i8* %.08, align 1
+ %9 = getelementptr inbounds i8* %.08, i64 1
+ store i8 %8, i8* %9, align 1
+ %10 = getelementptr inbounds i8* %.08, i64 2
+ %11 = add nsw i32 %.09, -1
+ %12 = icmp eq i32 %11, 0
+ br i1 %12, label %13, label %1
+
+; <label>:13
+ ret void
+}
+
+; Make sure that we merge the consecutive load/store sequence below and use a
+; word (16 bit) instead of a byte copy even if there are intermediate sign
+; extensions.
+; CHECK: MergeLoadStoreBaseIndexOffsetSext
+; CHECK: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]]
+; CHECK: movw [[REG]], (%{{.*}})
+define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) {
+ br label %1
+
+; <label>:1
+ %.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
+ %.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
+ %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
+ %2 = getelementptr inbounds i8* %.0, i64 1
+ %3 = load i8* %.0, align 1
+ %4 = sext i8 %3 to i64
+ %5 = getelementptr inbounds i8* %c, i64 %4
+ %6 = load i8* %5, align 1
+ %7 = add i64 %4, 1
+ %8 = getelementptr inbounds i8* %c, i64 %7
+ %9 = load i8* %8, align 1
+ store i8 %6, i8* %.08, align 1
+ %10 = getelementptr inbounds i8* %.08, i64 1
+ store i8 %9, i8* %10, align 1
+ %11 = getelementptr inbounds i8* %.08, i64 2
+ %12 = add nsw i32 %.09, -1
+ %13 = icmp eq i32 %12, 0
+ br i1 %13, label %14, label %1
+
+; <label>:14
+ ret void
+}
+
+; However, we can only merge ignore sign extensions when they are on all memory
+; computations;
+; CHECK: loadStoreBaseIndexOffsetSextNoSex
+; CHECK-NOT: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]]
+; CHECK-NOT: movw [[REG]], (%{{.*}})
+define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) {
+ br label %1
+
+; <label>:1
+ %.09 = phi i32 [ %n, %0 ], [ %12, %1 ]
+ %.08 = phi i8* [ %b, %0 ], [ %11, %1 ]
+ %.0 = phi i8* [ %a, %0 ], [ %2, %1 ]
+ %2 = getelementptr inbounds i8* %.0, i64 1
+ %3 = load i8* %.0, align 1
+ %4 = sext i8 %3 to i64
+ %5 = getelementptr inbounds i8* %c, i64 %4
+ %6 = load i8* %5, align 1
+ %7 = add i8 %3, 1
+ %wrap.4 = sext i8 %7 to i64
+ %8 = getelementptr inbounds i8* %c, i64 %wrap.4
+ %9 = load i8* %8, align 1
+ store i8 %6, i8* %.08, align 1
+ %10 = getelementptr inbounds i8* %.08, i64 1
+ store i8 %9, i8* %10, align 1
+ %11 = getelementptr inbounds i8* %.08, i64 2
+ %12 = add nsw i32 %.09, -1
+ %13 = icmp eq i32 %12, 0
+ br i1 %13, label %14, label %1
+
+; <label>:14
+ ret void
+}
projects / oota-llvm.git / blobdiff