[AVX512] Enabling bit logic lowering

[oota-llvm.git] / test / CodeGen / X86 / 2009-06-05-VZextByteShort.ll

diff --git a/test/CodeGen/X86/2009-06-05-VZextByteShort.ll b/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
index 1d29fea30d7de9eb141049f5526b52193ab28e59..ffbe02c713561e5229e2e6d0ecadaf195a0d3000 100644 (file)
--- a/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
+++ b/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
@@ -1,8 +1,11 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s
 
 define <4 x i16> @a(i32* %x1) nounwind {
-; CHECK:      movzx
-; CHECK-NEXT: movd
+; CHECK-LABEL: a:
+; CHECK:         shrl %[[R:[^,]+]]
+; CHECK-NEXT:    movd %[[R]], %xmm0
+; CHECK-NEXT:    retl
+
   %x2 = load i32* %x1
   %x3 = lshr i32 %x2, 1
   %x = trunc i32 %x3 to i16
@@ -11,8 +14,12 @@ define <4 x i16> @a(i32* %x1) nounwind {
 }
 
 define <8 x i16> @b(i32* %x1) nounwind {
-; CHECK:      movzx
-; CHECK-NEXT: movd
+; CHECK-LABEL: b:
+; CHECK:         shrl %e[[R:.]]x
+; CHECK-NEXT:    movzwl %[[R]]x, %e[[R]]x
+; CHECK-NEXT:    movd %e[[R]]x, %xmm0
+; CHECK-NEXT:    retl
+
   %x2 = load i32* %x1
   %x3 = lshr i32 %x2, 1
   %x = trunc i32 %x3 to i16
@@ -21,8 +28,12 @@ define <8 x i16> @b(i32* %x1) nounwind {
 }
 
 define <8 x i8> @c(i32* %x1) nounwind {
-; CHECK:      movzx
-; CHECK-NEXT: movd
+; CHECK-LABEL: c:
+; CHECK:         shrl %e[[R:.]]x
+; CHECK-NEXT:    movzwl %[[R]]x, %e[[R]]x
+; CHECK-NEXT:    movd %e[[R]]x, %xmm0
+; CHECK-NEXT:    retl
+
   %x2 = load i32* %x1
   %x3 = lshr i32 %x2, 1
   %x = trunc i32 %x3 to i8
@@ -31,8 +42,12 @@ define <8 x i8> @c(i32* %x1) nounwind {
 }
 
 define <16 x i8> @d(i32* %x1) nounwind {
-; CHECK:      movzx
-; CHECK-NEXT: movd
+; CHECK-LABEL: d:
+; CHECK:         shrl %e[[R:.]]x
+; CHECK-NEXT:    movzbl %[[R]]l, %e[[R]]x
+; CHECK-NEXT:    movd %e[[R]]x, %xmm0
+; CHECK-NEXT:    retl
+
   %x2 = load i32* %x1
   %x3 = lshr i32 %x2, 1
   %x = trunc i32 %x3 to i8