Test 221067 in a fixed-target test so as not to fail on targets with different DWARF...

[oota-llvm.git] / test / CodeGen / X86 / 2008-09-18-inline-asm-2.ll

diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
index dfd165cc03e657fd752bb5184fac8d259ecaea26..f4a43a1e978a21204d4b82b8a5e92c9fd933ba9f 100644 (file)
--- a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
+++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
@@ -1,7 +1,6 @@
-; RUN: llc < %s -march=x86 -regalloc=linearscan | FileCheck %s
-; RUN: llc < %s -march=x86 -regalloc=fast       | FileCheck %s
-; RUN: llc < %s -march=x86 -regalloc=basic      | FileCheck %s
-; RUN: llc < %s -march=x86 -regalloc=greedy     | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 -no-integrated-as | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=basic -no-integrated-as      | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=greedy -no-integrated-as     | FileCheck %s
 
 ; The 1st, 2nd, 3rd and 5th registers must all be different.  The registers
 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
@@ -18,7 +17,7 @@
 ; CHECK-NOT: [[A3]]
 ; CHECK: 5th=[[A5:%...]]
 ; CHECK-NOT: [[A1]]
-; CHECK-NOT; [[A5]]
+; CHECK-NOT: [[A5]]
 ; CHECK: =4th
 
 ; The 6th operand is an 8-bit register, and it mustn't alias the 1st and 5th.