TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFro...

[oota-llvm.git] / test / CodeGen / X86 / 2008-08-19-SubAndFetch.ll

diff --git a/test/CodeGen/X86/2008-08-19-SubAndFetch.ll b/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
index 00bcdf82e8ddda1009acec71bd2c785f7dbb6204..8475e8d354e5825c9b824dd1386df1f7e46a23c8 100644 (file)
--- a/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
+++ b/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
@@ -1,9 +1,12 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep xadd
+; RUN: llc < %s -march=x86-64 | FileCheck %s
 
 @var = external global i64             ; <i64*> [#uses=1]
 
 define i32 @main() nounwind {
 entry:
+; CHECK: main:
+; CHECK: lock
+; CHECK: decq
        tail call i64 @llvm.atomic.load.sub.i64.p0i64( i64* @var, i64 1 )               ; <i64>:0 [#uses=0]
        unreachable
 }