[PowerPC] Really iterate over all loops in PPCLoopDataPrefetch/PPCLoopPreIncPrep

[oota-llvm.git] / test / CodeGen / Thumb2 / thumb2-orn.ll

diff --git a/test/CodeGen/Thumb2/thumb2-orn.ll b/test/CodeGen/Thumb2/thumb2-orn.ll
index 92c4564841b9aa0d67103d0af28dd1314173dafa..e1f0bba7c4b86e0e3abb5b0f996a6c58fb303e42 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-orn.ll
+++ b/test/CodeGen/Thumb2/thumb2-orn.ll
@@ -1,32 +1,36 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 4
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
     %tmp = xor i32 %b, 4294967295
     %tmp1 = or i32 %a, %tmp
     ret i32 %tmp1
 }
+; CHECK-LABEL: f1:
+; CHECK:       orn     r0, r0, r1
 
 define i32 @f2(i32 %a, i32 %b) {
     %tmp = xor i32 %b, 4294967295
     %tmp1 = or i32 %tmp, %a
     ret i32 %tmp1
 }
+; CHECK-LABEL: f2:
+; CHECK:       orn     r0, r0, r1
 
 define i32 @f3(i32 %a, i32 %b) {
     %tmp = xor i32 4294967295, %b
     %tmp1 = or i32 %a, %tmp
     ret i32 %tmp1
 }
+; CHECK-LABEL: f3:
+; CHECK:       orn     r0, r0, r1
 
 define i32 @f4(i32 %a, i32 %b) {
     %tmp = xor i32 4294967295, %b
     %tmp1 = or i32 %tmp, %a
     ret i32 %tmp1
 }
+; CHECK-LABEL: f4:
+; CHECK:       orn     r0, r0, r1
 
 define i32 @f5(i32 %a, i32 %b) {
     %tmp = shl i32 %b, 5
@@ -34,6 +38,8 @@ define i32 @f5(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
+; CHECK-LABEL: f5:
+; CHECK:       orn     r0, r0, r1, lsl #5
 
 define i32 @f6(i32 %a, i32 %b) {
     %tmp = lshr i32 %b, 6
@@ -41,6 +47,8 @@ define i32 @f6(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
+; CHECK-LABEL: f6:
+; CHECK:       orn     r0, r0, r1, lsr #6
 
 define i32 @f7(i32 %a, i32 %b) {
     %tmp = ashr i32 %b, 7
@@ -48,6 +56,8 @@ define i32 @f7(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
+; CHECK-LABEL: f7:
+; CHECK:       orn     r0, r0, r1, asr #7
 
 define i32 @f8(i32 %a, i32 %b) {
     %l8 = shl i32 %a, 24
@@ -57,3 +67,5 @@ define i32 @f8(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
+; CHECK-LABEL: f8:
+; CHECK:       orn     r0, r0, r0, ror #8