ARM: Thumb2 LDRD/STRD supports independent input/output regs

[oota-llvm.git] / test / CodeGen / Thumb2 / thumb2-cmn.ll

diff --git a/test/CodeGen/Thumb2/thumb2-cmn.ll b/test/CodeGen/Thumb2/thumb2-cmn.ll
index 401c56a721393f21c122a9524930ccd5c4e8f09d..0f361d75e52c3f14c3db5e5985cbcbfe7a32cd65 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-cmn.ll
+++ b/test/CodeGen/Thumb2/thumb2-cmn.ll
@@ -1,32 +1,39 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
+
+; These tests could be improved by 'movs r0, #0' being rematerialized below the
+; test as 'mov.w r0, #0'.
 
 define i1 @f1(i32 %a, i32 %b) {
     %nb = sub i32 0, %b
     %tmp = icmp ne i32 %a, %nb
     ret i1 %tmp
 }
+; CHECK-LABEL: f1:
+; CHECK:       cmn     {{.*}}, r1
 
 define i1 @f2(i32 %a, i32 %b) {
     %nb = sub i32 0, %b
     %tmp = icmp ne i32 %nb, %a
     ret i1 %tmp
 }
+; CHECK-LABEL: f2:
+; CHECK:       cmn     {{.*}}, r1
 
 define i1 @f3(i32 %a, i32 %b) {
     %nb = sub i32 0, %b
     %tmp = icmp eq i32 %a, %nb
     ret i1 %tmp
 }
+; CHECK-LABEL: f3:
+; CHECK:       cmn     {{.*}}, r1
 
 define i1 @f4(i32 %a, i32 %b) {
     %nb = sub i32 0, %b
     %tmp = icmp eq i32 %nb, %a
     ret i1 %tmp
 }
+; CHECK-LABEL: f4:
+; CHECK:       cmn     {{.*}}, r1
 
 define i1 @f5(i32 %a, i32 %b) {
     %tmp = shl i32 %b, 5
@@ -34,6 +41,8 @@ define i1 @f5(i32 %a, i32 %b) {
     %tmp1 = icmp eq i32 %nb, %a
     ret i1 %tmp1
 }
+; CHECK-LABEL: f5:
+; CHECK:       cmn.w   {{.*}}, r1, lsl #5
 
 define i1 @f6(i32 %a, i32 %b) {
     %tmp = lshr i32 %b, 6
@@ -41,6 +50,8 @@ define i1 @f6(i32 %a, i32 %b) {
     %tmp1 = icmp ne i32 %nb, %a
     ret i1 %tmp1
 }
+; CHECK-LABEL: f6:
+; CHECK:       cmn.w   {{.*}}, r1, lsr #6
 
 define i1 @f7(i32 %a, i32 %b) {
     %tmp = ashr i32 %b, 7
@@ -48,6 +59,8 @@ define i1 @f7(i32 %a, i32 %b) {
     %tmp1 = icmp eq i32 %a, %nb
     ret i1 %tmp1
 }
+; CHECK-LABEL: f7:
+; CHECK:       cmn.w   {{.*}}, r1, asr #7
 
 define i1 @f8(i32 %a, i32 %b) {
     %l8 = shl i32 %a, 24
@@ -57,3 +70,16 @@ define i1 @f8(i32 %a, i32 %b) {
     %tmp1 = icmp ne i32 %a, %nb
     ret i1 %tmp1
 }
+; CHECK-LABEL: f8:
+; CHECK:       cmn.w   {{.*}}, {{.*}}, ror #8
+
+
+define void @f9(i32 %a, i32 %b) nounwind optsize {
+  tail call void asm sideeffect "cmn.w     r0, r1", ""() nounwind, !srcloc !0
+  ret void
+}
+
+!0 = !{i32 81}
+
+; CHECK-LABEL: f9:
+; CHECK:       cmn.w   r0, r1