[ARM] Enable shrink-wrapping by default.

[oota-llvm.git] / test / CodeGen / Thumb2 / thumb2-bcc.ll

diff --git a/test/CodeGen/Thumb2/thumb2-bcc.ll b/test/CodeGen/Thumb2/thumb2-bcc.ll
index bd40e3bf28cbae9fe0a2315b785b30881da6da74..e7b38221b00d13562dfe1c3cb1aadac48075fd3e 100644 (file)
--- a/test/CodeGen/Thumb2/thumb2-bcc.ll
+++ b/test/CodeGen/Thumb2/thumb2-bcc.ll
@@ -1,19 +1,23 @@
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
-; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep it
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
+; If-conversion defeats the purpose of this test, which is to check CBZ
+; generation, so use memory barrier instruction to make sure it doesn't
+; happen and we get actual branches.
 
 define i32 @t1(i32 %a, i32 %b, i32 %c) {
-; CHECK: t1
-; CHECK: beq
-       %tmp2 = icmp eq i32 %a, 0
-       br i1 %tmp2, label %cond_false, label %cond_true
+; CHECK-LABEL: t1:
+; CHECK: cbz
+  %tmp2 = icmp eq i32 %a, 0
+  br i1 %tmp2, label %cond_false, label %cond_true
 
 cond_true:
-       %tmp5 = add i32 %b, 1
-        %tmp6 = and i32 %tmp5, %c
-       ret i32 %tmp6
+  fence seq_cst
+  %tmp5 = add i32 %b, 1
+  %tmp6 = and i32 %tmp5, %c
+  ret i32 %tmp6
 
 cond_false:
-       %tmp7 = add i32 %b, -1
-        %tmp8 = xor i32 %tmp7, %c
-       ret i32 %tmp8
+  fence seq_cst
+  %tmp7 = add i32 %b, -1
+  %tmp8 = xor i32 %tmp7, %c
+  ret i32 %tmp8
 }