ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually test...

[oota-llvm.git] / test / CodeGen / Thumb2 / 2009-08-07-NeonFPBug.ll

diff --git a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
index 29e5ed382d4032c0a64cbc94e0b6ac24e7fd20a3..5480868d7a6685ff3411778f253a73c509ca360c 100644 (file)
--- a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
+++ b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -mattr=+neonfp
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8
 
        %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
        %struct.JHUFF_TBL = type { [17 x i8], [256 x i8], i32 }
@@ -28,17 +28,17 @@
        %struct.jvirt_barray_control = type { [64 x i16]**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_barray_control*, %struct.backing_store_info }
        %struct.jvirt_sarray_control = type { i8**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_sarray_control*, %struct.backing_store_info }
 
-define arm_apcscc void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind {
+define void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind {
 entry:
        br label %bb
 
 bb:            ; preds = %bb, %entry
-       %0 = load float* undef, align 4         ; <float> [#uses=1]
+       %0 = load float, float* undef, align 4          ; <float> [#uses=1]
        %1 = fmul float undef, %0               ; <float> [#uses=2]
        %tmp73 = add i32 0, 224         ; <i32> [#uses=1]
-       %scevgep74 = getelementptr i8* null, i32 %tmp73         ; <i8*> [#uses=1]
+       %scevgep74 = getelementptr i8, i8* null, i32 %tmp73             ; <i8*> [#uses=1]
        %scevgep7475 = bitcast i8* %scevgep74 to float*         ; <float*> [#uses=1]
-       %2 = load float* null, align 4          ; <float> [#uses=1]
+       %2 = load float, float* null, align 4           ; <float> [#uses=1]
        %3 = fmul float 0.000000e+00, %2                ; <float> [#uses=2]
        %4 = fadd float %1, %3          ; <float> [#uses=1]
        %5 = fsub float %1, %3          ; <float> [#uses=2]
@@ -51,7 +51,7 @@ bb:           ; preds = %bb, %entry
        %12 = sitofp i16 undef to float         ; <float> [#uses=1]
        %13 = fmul float %12, 0.000000e+00              ; <float> [#uses=2]
        %14 = sitofp i16 undef to float         ; <float> [#uses=1]
-       %15 = load float* %scevgep7475, align 4         ; <float> [#uses=1]
+       %15 = load float, float* %scevgep7475, align 4          ; <float> [#uses=1]
        %16 = fmul float %14, %15               ; <float> [#uses=2]
        %17 = fadd float undef, undef           ; <float> [#uses=2]
        %18 = fadd float %13, %16               ; <float> [#uses=2]