; Check the low end of the SH range.
define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sh %r2, 0(%r3)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the aligned SH range.
define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sh %r2, 4094(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2047
; Check the next halfword up, which should use SHY instead of SH.
define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: shy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2048
; Check the high end of the aligned SHY range.
define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: shy %r2, 524286(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r3, 524288
; CHECK: sh %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned SHY range.
define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: shy %r2, -2(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the SHY range.
define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: shy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, -524290
; CHECK: sh %r2, 0(%r3)
; CHECK: br %r14
; Check that SH allows an index.
define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: sh %r2, 4094({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%sub1 = add i64 %src, %index
; Check that SHY allows an index.
define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: shy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%sub1 = add i64 %src, %index