[SystemZ] Also clear kill flag for index reg in splitMove().

[oota-llvm.git] / test / CodeGen / SystemZ / int-cmp-37.ll

diff --git a/test/CodeGen/SystemZ/int-cmp-37.ll b/test/CodeGen/SystemZ/int-cmp-37.ll
index 272df713136b55c836e585611fa8d0b574a2d300..ac5d39f965111dc6c76c56fa367809b3be000063 100644 (file)
--- a/test/CodeGen/SystemZ/int-cmp-37.ll
+++ b/test/CodeGen/SystemZ/int-cmp-37.ll
@@ -8,12 +8,12 @@
 
 ; Check unsigned comparison.
 define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -27,11 +27,11 @@ exit:
 
 ; Check signed comparison.
 define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: clhrl
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -45,12 +45,12 @@ exit:
 
 ; Check equality.
 define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp eq i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -64,12 +64,12 @@ exit:
 
 ; Check inequality.
 define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@g
+  %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp ne i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -83,14 +83,13 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
-; CHECK: clr %r2, [[VAL]]
-; CHECK-NEXT: jl
+; CHECK: clrjl %r2, [[VAL]],
 ; CHECK: br %r14
 entry:
-  %val = load i16 *@h, align 1
+  %val = load i16 , i16 *@h, align 1
   %src2 = zext i16 %val to i32
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
@@ -101,3 +100,22 @@ exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
+
+; Check the comparison can be reversed if that allows CLHRL to be used.
+define i32 @f6(i32 %src2) {
+; CHECK-LABEL: f6:
+; CHECK: clhrl %r2, g
+; CHECK-NEXT: jh {{\.L.*}}
+; CHECK: br %r14
+entry:
+  %val = load i16 , i16 *@g
+  %src1 = zext i16 %val to i32
+  %cond = icmp ult i32 %src1, %src2
+  br i1 %cond, label %exit, label %mulb
+mulb:
+  %mul = mul i32 %src2, %src2
+  br label %exit
+exit:
+  %res = phi i32 [ %src2, %entry ], [ %mul, %mulb ]
+  ret i32 %res
+}