[Stack realignment] Handling of aligned allocas.

[oota-llvm.git] / test / CodeGen / SystemZ / int-cmp-04.ll

diff --git a/test/CodeGen/SystemZ/int-cmp-04.ll b/test/CodeGen/SystemZ/int-cmp-04.ll
index d0625fbddbae90923b8614ab3f308165a1f641b5..90f05ea386809e86ea77495ef2f88e1a3b2e8cc4 100644 (file)
--- a/test/CodeGen/SystemZ/int-cmp-04.ll
+++ b/test/CodeGen/SystemZ/int-cmp-04.ll
@@ -5,10 +5,10 @@
 
 ; Check CGH with no displacement.
 define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
-  %half = load i16 *%src
+  %half = load i16 , i16 *%src
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -18,11 +18,11 @@ define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the high end of the aligned CGH range.
 define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgh %r2, 524286(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262143
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262143
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -33,12 +33,12 @@ define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -48,11 +48,11 @@ define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the high end of the negative aligned CGH range.
 define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cgh %r2, -2(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -1
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -1
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -62,11 +62,11 @@ define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the low end of the CGH range.
 define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgh %r2, -524288(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262144
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262144
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -77,12 +77,12 @@ define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, -524290
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
-  %ptr = getelementptr i16 *%src, i64 -262145
-  %half = load i16 *%ptr
+  %ptr = getelementptr i16, i16 *%src, i64 -262145
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
@@ -92,16 +92,30 @@ define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check that CGH allows an index.
 define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cgh %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i16 *
-  %half = load i16 *%ptr
+  %half = load i16 , i16 *%ptr
   %rhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, i64 100, i64 200
   store i64 %res, i64 *%dst
   ret void
 }
+
+; Check the comparison can be reversed if that allows CGH to be used.
+define double @f8(double %a, double %b, i64 %rhs, i16 *%src) {
+; CHECK-LABEL: f8:
+; CHECK: cgh %r2, 0(%r3)
+; CHECK-NEXT: jh {{\.L.*}}
+; CHECK: ldr %f0, %f2
+; CHECK: br %r14
+  %half = load i16 , i16 *%src
+  %lhs = sext i16 %half to i64
+  %cond = icmp slt i64 %lhs, %rhs
+  %res = select i1 %cond, double %a, double %b
+  ret double %res
+}