[SystemZ] Add CodeGen support for scalar f64 ops in vector registers

[oota-llvm.git] / test / CodeGen / SystemZ / frame-17.ll

diff --git a/test/CodeGen/SystemZ/frame-17.ll b/test/CodeGen/SystemZ/frame-17.ll
index 485297a2b21dbca54ad4ae153d84160612cd1704..502e541bafc19c7eaa3afce7e50ff2f31cb724e5 100644 (file)
--- a/test/CodeGen/SystemZ/frame-17.ll
+++ b/test/CodeGen/SystemZ/frame-17.ll
@@ -1,6 +1,6 @@
 ; Test spilling of FPRs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; We need to save and restore 8 of the 16 FPRs and allocate an additional
 ; 4-byte spill slot, rounded to 8 bytes.  The frame size should be exactly