[Sparc] Use correct alignment while loading/storing fp128 values.

[oota-llvm.git] / test / CodeGen / SPARC / 64bit.ll

diff --git a/test/CodeGen/SPARC/64bit.ll b/test/CodeGen/SPARC/64bit.ll
index e10237b7d8ad1d2dae9f2909e7c306258fec09d9..f778f9dcf9a7496baef7004165a345d0896e6f55 100644 (file)
--- a/test/CodeGen/SPARC/64bit.ll
+++ b/test/CodeGen/SPARC/64bit.ll
@@ -1,13 +1,22 @@
-; RUN: llc < %s -march=sparcv9 | FileCheck %s
+; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
+; RUN: llc < %s -march=sparcv9  | FileCheck %s -check-prefix=OPT
 
-; CHECK: ret2:
+; CHECK-LABEL: ret2:
 ; CHECK: or %g0, %i1, %i0
+
+; OPT-LABEL: ret2:
+; OPT: jmp %o7+8
+; OPT: or %g0, %o1, %o0
 define i64 @ret2(i64 %a, i64 %b) {
   ret i64 %b
 }
 
 ; CHECK: shl_imm
 ; CHECK: sllx %i0, 7, %i0
+
+; OPT-LABEL: shl_imm:
+; OPT: jmp %o7+8
+; OPT: sllx %o0, 7, %o0
 define i64 @shl_imm(i64 %a) {
   %x = shl i64 %a, 7
   ret i64 %x
@@ -15,6 +24,10 @@ define i64 @shl_imm(i64 %a) {
 
 ; CHECK: sra_reg
 ; CHECK: srax %i0, %i1, %i0
+
+; OPT-LABEL: sra_reg:
+; OPT: jmp %o7+8
+; OPT: srax %o0, %o1, %o0
 define i64 @sra_reg(i64 %a, i64 %b) {
   %x = ashr i64 %a, %b
   ret i64 %x
@@ -27,12 +40,20 @@ define i64 @sra_reg(i64 %a, i64 %b) {
 ;
 ; CHECK: ret_imm0
 ; CHECK: or %g0, 0, %i0
+
+; OPT: ret_imm0
+; OPT: jmp %o7+8
+; OPT: or %g0, 0, %o0
 define i64 @ret_imm0() {
   ret i64 0
 }
 
 ; CHECK: ret_simm13
 ; CHECK: or %g0, -4096, %i0
+
+; OPT:   ret_simm13
+; OPT:   jmp %o7+8
+; OPT:   or %g0, -4096, %o0
 define i64 @ret_simm13() {
   ret i64 -4096
 }
@@ -41,13 +62,23 @@ define i64 @ret_simm13() {
 ; CHECK: sethi 4, %i0
 ; CHECK-NOT: or
 ; CHECK: restore
+
+; OPT:  ret_sethi
+; OPT:  jmp %o7+8
+; OPT:  sethi 4, %o0
 define i64 @ret_sethi() {
   ret i64 4096
 }
 
-; CHECK: ret_sethi
+; CHECK: ret_sethi_or
 ; CHECK: sethi 4, [[R:%[goli][0-7]]]
 ; CHECK: or [[R]], 1, %i0
+
+; OPT: ret_sethi_or
+; OPT: sethi 4, [[R:%[go][0-7]]]
+; OPT: jmp %o7+8
+; OPT: or [[R]], 1, %o0
+
 define i64 @ret_sethi_or() {
   ret i64 4097
 }
@@ -55,6 +86,12 @@ define i64 @ret_sethi_or() {
 ; CHECK: ret_nimm33
 ; CHECK: sethi 4, [[R:%[goli][0-7]]]
 ; CHECK: xor [[R]], -4, %i0
+
+; OPT: ret_nimm33
+; OPT: sethi 4, [[R:%[go][0-7]]]
+; OPT: jmp %o7+8
+; OPT: xor [[R]], -4, %o0
+
 define i64 @ret_nimm33() {
   ret i64 -4100
 }
@@ -124,6 +161,14 @@ define i64 @loads(i64* %p, i32* %q, i32* %r, i16* %s) {
   ret i64 %x3
 }
 
+; CHECK: load_bool
+; CHECK: ldub [%i0], %i0
+define i64 @load_bool(i1* %p) {
+  %a = load i1* %p
+  %b = zext i1 %a to i64
+  ret i64 %b
+}
+
 ; CHECK: stores
 ; CHECK: ldx [%i0+8], [[R:%[goli][0-7]]]
 ; CHECK: stx [[R]], [%i0+16]
@@ -193,7 +238,7 @@ entry:
 declare void @g(i8*)
 
 ; CHECK: expand_setcc
-; CHECK: subcc %i0, 1,
+; CHECK: cmp %i0, 1
 ; CHECK: movl %xcc, 1,
 define i32 @expand_setcc(i64 %a) {
   %cond = icmp sle i64 %a, 0
@@ -201,3 +246,42 @@ define i32 @expand_setcc(i64 %a) {
   %RV = sub i32 1, %cast2
   ret i32 %RV
 }
+
+; CHECK: spill_i64
+; CHECK: stx
+; CHECK: ldx
+define i64 @spill_i64(i64 %x) {
+  call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7}"()
+  ret i64 %x
+}
+
+; CHECK: bitcast_i64_f64
+; CHECK: std
+; CHECK: ldx
+define i64 @bitcast_i64_f64(double %x) {
+  %y = bitcast double %x to i64
+  ret i64 %y
+}
+
+; CHECK: bitcast_f64_i64
+; CHECK: stx
+; CHECK: ldd
+define double @bitcast_f64_i64(i64 %x) {
+  %y = bitcast i64 %x to double
+  ret double %y
+}
+
+; CHECK-LABEL: store_zero:
+; CHECK: stx %g0, [%i0]
+; CHECK: stx %g0, [%i1+8]
+
+; OPT-LABEL:  store_zero:
+; OPT:  stx %g0, [%o0]
+; OPT:  stx %g0, [%o1+8]
+define i64 @store_zero(i64* nocapture %a, i64* nocapture %b) {
+entry:
+  store i64 0, i64* %a, align 8
+  %0 = getelementptr inbounds i64* %b, i32 1
+  store i64 0, i64* %0, align 8
+  ret i64 0
+}