R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*

[oota-llvm.git] / test / CodeGen / R600 / unaligned-load-store.ll

diff --git a/test/CodeGen/R600/unaligned-load-store.ll b/test/CodeGen/R600/unaligned-load-store.ll
index d887594e42f5b2705940e007e05d8c378746adf7..4df69d1e5f1665ba1e5a507b6bb3c9facef31191 100644 (file)
--- a/test/CodeGen/R600/unaligned-load-store.ll
+++ b/test/CodeGen/R600/unaligned-load-store.ll
@@ -1,8 +1,7 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
 ; SI-LABEL: @unaligned_load_store_i32:
-; SI: V_ADD_I32_e64 [[REG:VGPR[0-9]+]]
-; DS_READ_U8 {{VGPR[0-9]+}}, 0, [[REG]]
+; DS_READ_U32 {{v[0-9]+}}, 0, [[REG]]
 define void @unaligned_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind {
   %v = load i32 addrspace(3)* %p, align 1
   store i32 %v, i32 addrspace(3)* %r, align 1
@@ -10,8 +9,7 @@ define void @unaligned_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r
 }
 
 ; SI-LABEL: @unaligned_load_store_v4i32:
-; SI: V_ADD_I32_e64 [[REG:VGPR[0-9]+]]
-; DS_READ_U8 {{VGPR[0-9]+}}, 0, [[REG]]
+; DS_READ_U32 {{v[0-9]+}}, 0, [[REG]]
 define void @unaligned_load_store_v4i32(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind {
   %v = load <4 x i32> addrspace(3)* %p, align 1
   store <4 x i32> %v, <4 x i32> addrspace(3)* %r, align 1