R600/SI: Allow using f32 rcp / rsq when denormals not handled.

[oota-llvm.git] / test / CodeGen / R600 / llvm.AMDGPU.rcp.ll

diff --git a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
index 42910a99afde8a13f61e706e17328863c788c976..8d5d66e149ba450d184391aff56e21690a5d57da 100644 (file)
--- a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
@@ -1,5 +1,7 @@
-; RUN: llc -march=r600 -mcpu=SI -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=SI -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
+
+; XUN: llc -march=r600 -mcpu=SI -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s
 
 declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone
 declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone
@@ -25,15 +27,8 @@ define void @rcp_f64(double addrspace(1)* %out, double %src) nounwind {
 }
 
 ; FUNC-LABEL: @rcp_pat_f32
-; SI-UNSAFE-NOT: V_MUL_F32
-; SI-UNSAFE: V_RCP_F32_e32
-; SI-UNSAFE-NOT: V_MUL_F32
-
-; Check for surrounding multiplies the correct divide has.
-; SI-SAFE: V_MUL_F32
 ; SI-SAFE: V_RCP_F32_e32
-; SI-SAFE: V_MUL_F32
-
+; XSI-SAFE-SPDENORM-NOT: V_RCP_F32_e32
 define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
   %rcp = fdiv float 1.0, %src
   store float %rcp, float addrspace(1)* %out, align 4
@@ -60,7 +55,8 @@ define void @rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
 }
 
 ; FUNC-LABEL: @rsq_rcp_pat_f64
-; SI: V_RSQ_F64_e32
+; SI-UNSAFE: V_RSQ_F64_e32
+; SI-SAFE-NOT: V_RSQ_F64_e32
 define void @rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind {
   %sqrt = call double @llvm.sqrt.f64(double %src) nounwind readnone
   %rcp = call double @llvm.AMDGPU.rcp.f64(double %sqrt) nounwind readnone