llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll: s/REQUIRE/REQUIRES/

[oota-llvm.git] / test / CodeGen / PowerPC / vec_misaligned.ll

diff --git a/test/CodeGen/PowerPC/vec_misaligned.ll b/test/CodeGen/PowerPC/vec_misaligned.ll
index d7ed64a5b1cfcfa2fc799e5873de2b2fbbc22bdb..ac639d71991189ff8a2ccfdd1edfa078795ffc0b 100644 (file)
--- a/test/CodeGen/PowerPC/vec_misaligned.ll
+++ b/test/CodeGen/PowerPC/vec_misaligned.ll
@@ -1,4 +1,6 @@
-; RUN: llc < %s -march=ppc32 -mcpu=g5
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-vector | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-vector | FileCheck %s -check-prefix=CHECK-LE
 
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
 target triple = "powerpc-apple-darwin8"
@@ -8,6 +10,8 @@ target triple = "powerpc-apple-darwin8"
 
 define void @foo(i32 %x, ...) {
 entry:
+; CHECK: foo:
+; CHECK-LE: foo:
        %x_addr = alloca i32            ; <i32*> [#uses=1]
        %ap = alloca i8*                ; <i8**> [#uses=3]
        %ap.0 = alloca i8*              ; <i8**> [#uses=3]
@@ -15,18 +19,22 @@ entry:
        store i32 %x, i32* %x_addr
        %ap1 = bitcast i8** %ap to i8*          ; <i8*> [#uses=1]
        call void @llvm.va_start( i8* %ap1 )
-       %tmp = load i8** %ap, align 4           ; <i8*> [#uses=1]
+       %tmp = load i8*, i8** %ap, align 4              ; <i8*> [#uses=1]
        store i8* %tmp, i8** %ap.0, align 4
-       %tmp2 = load i8** %ap.0, align 4                ; <i8*> [#uses=1]
-       %tmp3 = getelementptr i8* %tmp2, i64 16         ; <i8*> [#uses=1]
+       %tmp2 = load i8*, i8** %ap.0, align 4           ; <i8*> [#uses=1]
+       %tmp3 = getelementptr i8, i8* %tmp2, i64 16             ; <i8*> [#uses=1]
        store i8* %tmp3, i8** %ap, align 4
-       %tmp4 = load i8** %ap.0, align 4                ; <i8*> [#uses=1]
+       %tmp4 = load i8*, i8** %ap.0, align 4           ; <i8*> [#uses=1]
        %tmp45 = bitcast i8* %tmp4 to %struct.S2203*            ; <%struct.S2203*> [#uses=1]
-       %tmp6 = getelementptr %struct.S2203* @s, i32 0, i32 0           ; <%struct.u16qi*> [#uses=1]
-       %tmp7 = getelementptr %struct.S2203* %tmp45, i32 0, i32 0               ; <%struct.u16qi*> [#uses=1]
-       %tmp8 = getelementptr %struct.u16qi* %tmp6, i32 0, i32 0                ; <<16 x i8>*> [#uses=1]
-       %tmp9 = getelementptr %struct.u16qi* %tmp7, i32 0, i32 0                ; <<16 x i8>*> [#uses=1]
-       %tmp10 = load <16 x i8>* %tmp9, align 4         ; <<16 x i8>> [#uses=1]
+       %tmp6 = getelementptr %struct.S2203, %struct.S2203* @s, i32 0, i32 0            ; <%struct.u16qi*> [#uses=1]
+       %tmp7 = getelementptr %struct.S2203, %struct.S2203* %tmp45, i32 0, i32 0                ; <%struct.u16qi*> [#uses=1]
+       %tmp8 = getelementptr %struct.u16qi, %struct.u16qi* %tmp6, i32 0, i32 0         ; <<16 x i8>*> [#uses=1]
+       %tmp9 = getelementptr %struct.u16qi, %struct.u16qi* %tmp7, i32 0, i32 0         ; <<16 x i8>*> [#uses=1]
+       %tmp10 = load <16 x i8>, <16 x i8>* %tmp9, align 4              ; <<16 x i8>> [#uses=1]
+; CHECK: lvsl
+; CHECK: vperm
+; CHECK-LE: lvsr
+; CHECK-LE: vperm
        store <16 x i8> %tmp10, <16 x i8>* %tmp8, align 4
        br label %return