ret <2 x float> %fmuladd
}
; fmuladd (<2 x float>) is promoted to fmuladd (<4 x float>)
-; CHECK: v2f32_fmuladd:
+; CHECK-LABEL: v2f32_fmuladd:
; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
define <4 x float> @v4f32_fmuladd(<4 x float> %x) nounwind readnone {
%fmuladd = call <4 x float> @llvm.fmuladd.v4f32 (<4 x float> %x, <4 x float> %x, <4 x float> %x)
ret <4 x float> %fmuladd
}
-; CHECK: v4f32_fmuladd:
+; CHECK-LABEL: v4f32_fmuladd:
; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
define <8 x float> @v8f32_fmuladd(<8 x float> %x) nounwind readnone {
%fmuladd = call <8 x float> @llvm.fmuladd.v8f32 (<8 x float> %x, <8 x float> %x, <8 x float> %x)
ret <8 x float> %fmuladd
}
-; CHECK: v8f32_fmuladd:
+; CHECK-LABEL: v8f32_fmuladd:
; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%fmuladd = call <2 x double> @llvm.fmuladd.v2f64 (<2 x double> %x, <2 x double> %x, <2 x double> %x)
ret <2 x double> %fmuladd
}
-; CHECK: v2f64_fmuladd:
+; CHECK-LABEL: v2f64_fmuladd:
; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%fmuladd = call <4 x double> @llvm.fmuladd.v4f64 (<4 x double> %x, <4 x double> %x, <4 x double> %x)
ret <4 x double> %fmuladd
}
-; CHECK: v4f64_fmuladd:
+; CHECK-LABEL: v4f64_fmuladd:
; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}