enable PPC register scavenging by default (update tests and remove some FIXMEs)

[oota-llvm.git] / test / CodeGen / PowerPC / ppc32-vaarg.ll

diff --git a/test/CodeGen/PowerPC/ppc32-vaarg.ll b/test/CodeGen/PowerPC/ppc32-vaarg.ll
index 725c106dd6e42e0b74f342266b0b871f02dfc4c6..c2680fbca3e1d6b650326adc1ac5c801196d42d4 100644 (file)
--- a/test/CodeGen/PowerPC/ppc32-vaarg.ll
+++ b/test/CodeGen/PowerPC/ppc32-vaarg.ll
@@ -37,8 +37,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
 ; CHECK-NEXT: stw 3, -24(1)
 ; CHECK-NEXT: stw 8, -28(1)
 ; CHECK-NEXT: stw 6, -32(1)
-; CHECK-NEXT: mfcr 0                          # cr0
-; CHECK-NEXT: stw 0, -36(1)
+; CHECK-NEXT: mfcr 3                          # cr0
+; CHECK-NEXT: stw 3, -36(1)
 ; CHECK-NEXT: blt 0, .LBB0_4
 ; CHECK-NEXT: # BB#3:                                 # %entry
 ; CHECK-NEXT: lwz 3, -20(1)
@@ -82,8 +82,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
 ; CHECK-NEXT: stw 4, -52(1)
 ; CHECK-NEXT: stw 6, -56(1)
 ; CHECK-NEXT: stw 8, -60(1)
-; CHECK-NEXT: mfcr 0                          # cr0
-; CHECK-NEXT: stw 0, -64(1)
+; CHECK-NEXT: mfcr 3                          # cr0
+; CHECK-NEXT: stw 3, -64(1)
 ; CHECK-NEXT: blt 0, .LBB0_8
 ; CHECK-NEXT: # BB#7:                                 # %entry
 ; CHECK-NEXT: lwz 3, -48(1)
@@ -122,8 +122,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
 ; CHECK-NEXT: mr 8, 5
 ; CHECK-NEXT: stw 4, -72(1)
 ; CHECK-NEXT: stw 6, -76(1)
-; CHECK-NEXT: mfcr 0                          # cr0
-; CHECK-NEXT: stw 0, -80(1)
+; CHECK-NEXT: mfcr 3                          # cr0
+; CHECK-NEXT: stw 3, -80(1)
 ; CHECK-NEXT: stw 5, -84(1)
 ; CHECK-NEXT: stw 8, -88(1)
 ; CHECK-NEXT: stw 7, -92(1)