[PowerPC] MULHU/MULHS are not legal for vector types

[oota-llvm.git] / test / CodeGen / PowerPC / fp-branch.ll

diff --git a/test/CodeGen/PowerPC/fp-branch.ll b/test/CodeGen/PowerPC/fp-branch.ll
index 804cbf6f8cee8e4d88a7b3da0822e701c4a19990..673da027e229bc1b5fda66eacceaf81ff0b191cf 100644 (file)
--- a/test/CodeGen/PowerPC/fp-branch.ll
+++ b/test/CodeGen/PowerPC/fp-branch.ll
@@ -1,20 +1,21 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep fcmp | count 1
+; RUN: llc < %s -march=ppc32 | grep fcmp | count 1
 
-declare bool %llvm.isunordered.f64(double, double)
+declare i1 @llvm.isunordered.f64(double, double)
 
-bool %intcoord_cond_next55(double %tmp48.reload) {
+define i1 @intcoord_cond_next55(double %tmp48.reload) {
 newFuncRoot:
-       br label %cond_next55
+        br label %cond_next55
 
-bb72.exitStub:         ; preds = %cond_next55
-       ret bool true
+bb72.exitStub:          ; preds = %cond_next55
+        ret i1 true
 
-cond_next62.exitStub:          ; preds = %cond_next55
-       ret bool false
+cond_next62.exitStub:           ; preds = %cond_next55
+        ret i1 false
 
-cond_next55:           ; preds = %newFuncRoot
-       %tmp57 = setge double %tmp48.reload, 1.000000e+00               ; <bool> [#uses=1]
-       %tmp58 = tail call bool %llvm.isunordered.f64( double %tmp48.reload, double 1.000000e+00 )              ; <bool> [#uses=1]
-       %tmp59 = or bool %tmp57, %tmp58         ; <bool> [#uses=1]
-       br bool %tmp59, label %bb72.exitStub, label %cond_next62.exitStub
+cond_next55:            ; preds = %newFuncRoot
+        %tmp57 = fcmp oge double %tmp48.reload, 1.000000e+00            ; <i1> [#uses=1]
+        %tmp58 = fcmp uno double %tmp48.reload, 1.000000e+00            ; <i1> [#uses=1]
+        %tmp59 = or i1 %tmp57, %tmp58           ; <i1> [#uses=1]
+        br i1 %tmp59, label %bb72.exitStub, label %cond_next62.exitStub
 }
+