[NVPTX] Rename registers %fl -> %fd and %rl -> %rd

[oota-llvm.git] / test / CodeGen / NVPTX / load-sext-i1.ll

diff --git a/test/CodeGen/NVPTX/load-sext-i1.ll b/test/CodeGen/NVPTX/load-sext-i1.ll
index c9b2e9793bbce19e4e4704990e41c7dc4d5a96e0..d836740eed940e84f59ba7b2b6a1b079d6f95768 100644 (file)
--- a/test/CodeGen/NVPTX/load-sext-i1.ll
+++ b/test/CodeGen/NVPTX/load-sext-i1.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
-
+target triple = "nvptx-nvidia-cuda"
 
 define void @main(i1* %a1, i32 %a2, i32* %arg3) {
 ; CHECK: ld.u8