[mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.

[oota-llvm.git] / test / CodeGen / Mips / srl1.ll

diff --git a/test/CodeGen/Mips/srl1.ll b/test/CodeGen/Mips/srl1.ll
index 3474283faef9954cdab56f4a275c7a8f07603f17..8e97734bb313c75c579cfb31dc1292351b8f89be 100644 (file)
--- a/test/CodeGen/Mips/srl1.ll
+++ b/test/CodeGen/Mips/srl1.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
 
 @i = global i32 10654, align 4
 @j = global i32 0, align 4
@@ -6,12 +6,12 @@
 
 define i32 @main() nounwind {
 entry:
-  %0 = load i32* @i, align 4
+  %0 = load i32, i32* @i, align 4
   %shr = lshr i32 %0, 4
 ; 16:  srl     ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
   store i32 %shr, i32* @j, align 4
-  %1 = load i32* @j, align 4
-  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1)
+  %1 = load i32, i32* @j, align 4
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1)
   ret i32 0
 }