[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error...

[oota-llvm.git] / test / CodeGen / Mips / msa / elm_cxcmsa.ll

diff --git a/test/CodeGen/Mips/msa/elm_cxcmsa.ll b/test/CodeGen/Mips/msa/elm_cxcmsa.ll
index 383c4ae8b370292af624887704a9cf748e3986ab..dc1fcf79ca45d5ec8979e951cdbfc8bba522b79a 100644 (file)
--- a/test/CodeGen/Mips/msa/elm_cxcmsa.ll
+++ b/test/CodeGen/Mips/msa/elm_cxcmsa.ll
@@ -1,7 +1,7 @@
 ; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM
 ; instruction format).
 
-; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
 
 define i32 @msa_ir_cfcmsa_test() nounwind {
 entry: