[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error...

[oota-llvm.git] / test / CodeGen / Mips / msa / compare.ll

diff --git a/test/CodeGen/Mips/msa/compare.ll b/test/CodeGen/Mips/msa/compare.ll
index 2e66d9467da940f649eda258db5451cdd665530f..e45e84931a70bacf071124ba57efb2e5d8710421 100644 (file)
--- a/test/CodeGen/Mips/msa/compare.ll
+++ b/test/CodeGen/Mips/msa/compare.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
 
 define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: ceq_v16i8: