[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error...

[oota-llvm.git] / test / CodeGen / Mips / msa / arithmetic.ll

diff --git a/test/CodeGen/Mips/msa/arithmetic.ll b/test/CodeGen/Mips/msa/arithmetic.ll
index 7dc758e35dfc78938dc3388d2b7110ddd5a5ebee..dc655e184abf6584eede41aa2fc88a0c0cf5fe58 100644 (file)
--- a/test/CodeGen/Mips/msa/arithmetic.ll
+++ b/test/CodeGen/Mips/msa/arithmetic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
 
 define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: add_v16i8: