[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error...

[oota-llvm.git] / test / CodeGen / Mips / msa / 3rf_exdo.ll

diff --git a/test/CodeGen/Mips/msa/3rf_exdo.ll b/test/CodeGen/Mips/msa/3rf_exdo.ll
index d5713cb9aea8f4e4e3bc78e201f3100c254ae8f6..16a3c81841fe8030019ddd8b27b4e1056db60277 100644 (file)
--- a/test/CodeGen/Mips/msa/3rf_exdo.ll
+++ b/test/CodeGen/Mips/msa/3rf_exdo.ll
@@ -1,7 +1,7 @@
 ; Test the MSA floating-point conversion intrinsics that are encoded with the
 ; 3RF instruction format.
 
-; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
 
 @llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
 @llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16