MIPS DSP: add operands to make sure instruction strings are being matched.

[oota-llvm.git] / test / CodeGen / Mips / mips64instrs.ll

diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll
index 16bca0fbbf708ebc4482268e210ab29f34375493..041831149057e1dc35dfc8555bdb965f86c55dc6 100644 (file)
--- a/test/CodeGen/Mips/mips64instrs.ll
+++ b/test/CodeGen/Mips/mips64instrs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64el -mcpu=mips64r1 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
 
 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
 entry:
@@ -116,20 +116,28 @@ entry:
   ret i64 %rem
 }
 
-declare i64 @llvm.ctlz.i64(i64) nounwind readnone
+declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
 
-; CHECK: dclz $2, $4
 define i64 @f18(i64 %X) nounwind readnone {
 entry:
-  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X)
+; CHECK: dclz $2, $4
+  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
   ret i64 %tmp1
 }
 
-; CHECK: dclo $2, $4
 define i64 @f19(i64 %X) nounwind readnone {
 entry:
+; CHECK: dclo $2, $4
   %neg = xor i64 %X, -1
-  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg)
+  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
   ret i64 %tmp1
 }
 
+define i64 @f20(i64 %a, i64 %b) nounwind readnone {
+entry:
+; CHECK: nor
+  %or = or i64 %b, %a
+  %neg = xor i64 %or, -1
+  ret i64 %neg
+}
+