Re-apply r214881: Fix return sequence on armv4 thumb

[oota-llvm.git] / test / CodeGen / Mips / mips64ext.ll

diff --git a/test/CodeGen/Mips/mips64ext.ll b/test/CodeGen/Mips/mips64ext.ll
index 33af0d852daa20c833b5afb19d695b5646a0d9f1..22ea0eb7769ca452e2bbcb5f9e9638c043d75aa5 100644 (file)
--- a/test/CodeGen/Mips/mips64ext.ll
+++ b/test/CodeGen/Mips/mips64ext.ll
@@ -1,11 +1,27 @@
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s 
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -mattr=n64 | FileCheck %s
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s
 
 define i64 @zext64_32(i32 %a) nounwind readnone {
 entry:
 ; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2
-; CHECK: dsll32 $[[R1:[0-9]+]], $[[R0]], 0
-; CHECK: dsrl32  ${{[0-9]+}}, $[[R1]], 0
+; CHECK: dsll $[[R1:[0-9]+]], $[[R0]], 32
+; CHECK: dsrl ${{[0-9]+}}, $[[R1]], 32
   %add = add i32 %a, 2
   %conv = zext i32 %add to i64
   ret i64 %conv
 }
+
+define i64 @sext64_32(i32 %a) nounwind readnone {
+entry:
+; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0
+  %conv = sext i32 %a to i64
+  ret i64 %conv
+}
+
+define i64 @i64_float(float %f) nounwind readnone {
+entry:
+; CHECK: trunc.l.s 
+  %conv = fptosi float %f to i64
+  ret i64 %conv
+}
+