[mips] Correct 128-bit shifts on 64-bit targets.

[oota-llvm.git] / test / CodeGen / Mips / llvm-ir / shl.ll

diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll
index 90d59d75442910b8ff8914cc557b5d6689438826..bba34c47ea82711b98c4187458e8c6c916944e2c 100644 (file)
--- a/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -151,7 +151,7 @@ entry:
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsllv     $[[T1:[0-9]+]], $5, $7
-  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 32
+  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
   ; M3:             move      $2, $[[T1]]
   ; M3:             dsllv     $[[T4:[0-9]+]], $4, $7
@@ -174,7 +174,7 @@ entry:
   ; GP64-NOT-R6:    dsrlv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
   ; GP64-NOT-R6:    or        $2, $[[T0]], $[[T4]]
   ; GP64-NOT-R6:    dsllv     $3, $5, $7
-  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T2]], 32
+  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T2]], 64
   ; GP64-NOT-R6:    movn      $2, $3, $[[T5]]
   ; GP64-NOT-R6:    jr        $ra
   ; GP64-NOT-R6:    movn      $3, $zero, $1
@@ -185,7 +185,7 @@ entry:
   ; 64R6:           not       $[[T3:[0-9]+]], $[[T2]]
   ; 64R6:           dsrlv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
   ; 64R6:           or        $[[T5:[0-9]+]], $[[T0]], $[[T4]]
-  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T2]], 32
+  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T2]], 64
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
   ; 64R6:           dsllv     $[[T9:[0-9]+]], $5, $7