[mips] Correct 128-bit shifts on 64-bit targets.

[oota-llvm.git] / test / CodeGen / Mips / llvm-ir / lshr.ll

diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll
index 6fb59845f5b4884c23312f31efc76314fc745f48..3a7029fa5b7a79d8ec0aa4ad8def249aeab1a1ff 100644 (file)
--- a/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -139,7 +139,7 @@ entry:
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $7
-  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 32
+  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
   ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $7
@@ -162,7 +162,7 @@ entry:
   ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
   ; GP64-NOT-R6:    or        $3, $[[T4]], $[[T0]]
   ; GP64-NOT-R6:    dsrlv     $2, $4, $7
-  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T2]], 32
+  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T2]], 64
   ; GP64-NOT-R6:    movn      $3, $2, $[[T5]]
   ; GP64-NOT-R6:    jr        $ra
   ; GP64-NOT-R6:    movn      $2, $zero, $1
@@ -173,7 +173,7 @@ entry:
   ; 64R6:           not       $[[T3:[0-9]+]], $[[T2]]
   ; 64R6:           dsllv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
   ; 64R6:           or        $[[T5:[0-9]+]], $[[T4]], $[[T0]]
-  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T2]], 32
+  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T2]], 64
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
   ; 64R6:           dsrlv     $[[T9:[0-9]+]], $4, $7