%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: sccweqand:
+; CHECK-LABEL: sccweqand:
; CHECK: bit.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: rra.w r15
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: sccwneand:
+; CHECK-LABEL: sccwneand:
; CHECK: bit.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: and.w #1, r15
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwne:
+; CHECK-LABEL:sccwne:
; CHECK: cmp.w r14, r15
; CHECK: mov.w r2, r12
; CHECK: rra.w r12
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccweq:
+; CHECK-LABEL:sccweq:
; CHECK: cmp.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: rra.w r15
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwugt:
+; CHECK-LABEL:sccwugt:
; CHECK: cmp.w r15, r14
; CHECK: mov.w #1, r15
; CHECK: bic.w r2, r15
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwuge:
+; CHECK-LABEL:sccwuge:
; CHECK: cmp.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: and.w #1, r15
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwult:
+; CHECK-LABEL:sccwult:
; CHECK: cmp.w r14, r15
; CHECK: mov.w #1, r15
; CHECK: bic.w r2, r15
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwule:
+; CHECK-LABEL:sccwule:
; CHECK: cmp.w r15, r14
; CHECK: mov.w r2, r15
; CHECK: and.w #1, r15