MIR Parser: Implicit register verifier should accept unexpected implicit

[oota-llvm.git] / test / CodeGen / MIR / X86 / virtual-registers.mir

diff --git a/test/CodeGen/MIR/X86/virtual-registers.mir b/test/CodeGen/MIR/X86/virtual-registers.mir
index c6d76e6a18c5841429e897791504a4b54ecb3959..93c2fea6fd95a4a2faa4015b9b20043ae99d38c8 100644 (file)
--- a/test/CodeGen/MIR/X86/virtual-registers.mir
+++ b/test/CodeGen/MIR/X86/virtual-registers.mir
@@ -41,29 +41,27 @@ registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
   - { id: 2, class: gr32 }
-body:
-  - id:          0
-    name:        entry
-    # CHECK:      %0 = COPY %edi
-    # CHECK-NEXT: %1 = SUB32ri8 %0, 10
-    instructions:
-      - '%0 = COPY %edi'
-      - '%1 = SUB32ri8 %0, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit %eflags'
-      - 'JMP_1 %bb.1.less'
-  - id:          1
-    name:        less
-    # CHECK:      %2 = MOV32r0
-    # CHECK-NEXT: %eax = COPY %2
-    instructions:
-      - '%2 = MOV32r0 implicit-def %eflags'
-      - '%eax = COPY %2'
-      - 'RETQ %eax'
-  - id:          2
-    name:        exit
-    instructions:
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.exit, %bb.1.less
+    liveins: %edi
+    ; CHECK:      %0 = COPY %edi
+    ; CHECK-NEXT: %1 = SUB32ri8 %0, 10
+    %0 = COPY %edi
+    %1 = SUB32ri8 %0, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit %eflags
+    JMP_1 %bb.1.less
+
+  bb.1.less:
+    ; CHECK:      %2 = MOV32r0
+    ; CHECK-NEXT: %eax = COPY %2
+    %2 = MOV32r0 implicit-def %eflags
+    %eax = COPY %2
+    RETQ %eax
+
+  bb.2.exit:
+    %eax = COPY %0
+    RETQ %eax
 ...
 ---
 name:            foo
@@ -78,28 +76,26 @@ registers:
   - { id: 2, class: gr32 }
   - { id: 0, class: gr32 }
   - { id: 10, class: gr32 }
-body:
-  - id:          0
-    name:        entry
-    # CHECK:      %0 = COPY %edi
-    # CHECK-NEXT: %1 = SUB32ri8 %0, 10
-    instructions:
-      - '%2 = COPY %edi'
-      - '%0 = SUB32ri8 %2, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit %eflags'
-      - 'JMP_1 %bb.1.less'
-  - id:          1
-    name:        less
-    # CHECK:      %2 = MOV32r0
-    # CHECK-NEXT: %eax = COPY %2
-    instructions:
-      - '%10 = MOV32r0 implicit-def %eflags'
-      - '%eax = COPY %10'
-      - 'RETQ %eax'
-  - id:          2
-    name:        exit
-    # CHECK: %eax = COPY %0
-    instructions:
-      - '%eax = COPY %2'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.exit, %bb.1.less
+    liveins: %edi
+    ; CHECK:      %0 = COPY %edi
+    ; CHECK-NEXT: %1 = SUB32ri8 %0, 10
+    %2 = COPY %edi
+    %0 = SUB32ri8 %2, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit %eflags
+    JMP_1 %bb.1.less
+
+  bb.1.less:
+    ; CHECK:      %2 = MOV32r0
+    ; CHECK-NEXT: %eax = COPY %2
+    %10 = MOV32r0 implicit-def %eflags
+    %eax = COPY %10
+    RETQ %eax
+
+  bb.2.exit:
+    ; CHECK: %eax = COPY %0
+    %eax = COPY %2
+    RETQ %eax
 ...