MIR Serialization: Serialize the simple virtual register allocation hints.

[oota-llvm.git] / test / CodeGen / MIR / X86 / simple-register-allocation-hints.mir

diff --git a/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
new file mode 100644 (file)
index 0000000..42ed70e
--- /dev/null
+++ b/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
@@ -0,0 +1,35 @@
+# RUN: llc -march=x86-64 -start-after machine-scheduler -stop-after machine-scheduler -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses simple register allocation hints
+# correctly.
+
+--- |
+
+  define i32 @test(i32 %a, i32 %b) {
+  body:
+    %c = mul i32 %a, %b
+    ret i32 %c
+  }
+
+...
+---
+name:            test
+tracksRegLiveness: true
+# CHECK: registers:
+# CHECK-NEXT:  - { id: 0, class: gr32 }
+# CHECK-NEXT:  - { id: 1, class: gr32, preferred-register: '%esi' }
+# CHECK-NEXT:  - { id: 2, class: gr32, preferred-register: '%edi' }
+registers:
+  - { id: 0, class: gr32 }
+  - { id: 1, class: gr32, preferred-register: '%esi' }
+  - { id: 2, class: gr32, preferred-register: '%edi' }
+body:
+  - id:              0
+    name:            body
+    liveins:         [ '%edi', '%esi' ]
+    instructions:
+      - '%1 = COPY %esi'
+      - '%2 = COPY %edi'
+      - '%2 = IMUL32rr %2, %1, implicit-def dead %eflags'
+      - '%eax = COPY %2'
+      - 'RETQ killed %eax'
+...