-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon -disable-hexagon-misched < %s | FileCheck %s
; Check that we generate dual stores in one packet in V4
-; CHECK: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}
-; CHECK-NEXT: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}
-; CHECK-NEXT: }
+; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}=
+; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}=
-@Reg = global i32 0, align 4
-define void @foo() nounwind {
+define i32 @main(i32 %v, i32* %p1, i32* %p2) nounwind {
entry:
- %number= alloca i32, align 4
- store i32 500, i32* %number, align 4
- %number1= alloca i32, align 4
- store i32 100, i32* %number1, align 4
- ret void
+ store i32 %v, i32* %p1, align 4
+ store i32 %v, i32* %p2, align 4
+ ret i32 0
}
-