Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default

[oota-llvm.git] / test / CodeGen / Hexagon / doubleconvert-ieee-rnd-near.ll

diff --git a/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll b/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
index ff2f0e8a7b021c11c41cfe79df2594923b8673e3..6bf8224904ec03bad84d1cc7b07371ca7cd66902 100644 (file)
--- a/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
+++ b/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-hexagon-ieee-rnd-near < %s | FileCheck %s
-; Check that we generate conversion from double precision floating point 
+; Check that we generate conversion from double precision floating point
 ; to 32-bit int value in IEEE rounding to the nearest mode in V5.
 
 ; CHECK: r{{[0-9]+}} = convert_df2w(r{{[0-9]+}}:{{[0-9]+}})
@@ -14,13 +14,13 @@ entry:
   store i32 0, i32* %retval
   store double 1.540000e+01, double* %a, align 8
   store double 9.100000e+00, double* %b, align 8
-  %0 = load double* %a, align 8
-  %1 = load double* %b, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
   %add = fadd double %0, %1
   store double %add, double* %c, align 8
-  %2 = load double* %c, align 8
+  %2 = load double, double* %c, align 8
   %conv = fptosi double %2 to i32
   store i32 %conv, i32* %i, align 4
-  %3 = load i32* %i, align 4
+  %3 = load i32, i32* %i, align 4
   ret i32 %3
 }