AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.

[oota-llvm.git] / test / CodeGen / ARM64 / fp128.ll

diff --git a/test/CodeGen/ARM64/fp128.ll b/test/CodeGen/ARM64/fp128.ll
index d3ac28c5076afe8166e6abf339088eba52199494..57bbb93e12b747b96ed0ab71f64862c6a165dbef 100644 (file)
--- a/test/CodeGen/ARM64/fp128.ll
+++ b/test/CodeGen/ARM64/fp128.ll
@@ -133,7 +133,7 @@ define i1 @test_setcc1() {
   %val = fcmp ole fp128 %lhs, %rhs
 ; CHECK: bl __letf2
 ; CHECK: cmp w0, #0
-; CHECK: csinc w0, wzr, wzr, gt
+; CHECK: cset w0, le
 
   ret i1 %val
 ; CHECK: ret
@@ -150,11 +150,11 @@ define i1 @test_setcc2() {
   %val = fcmp ugt fp128 %lhs, %rhs
 ; CHECK: bl      __gttf2
 ; CHECK: cmp     w0, #0
-; CHECK: csinc   [[GT:w[0-9]+]], wzr, wzr, le
+; CHECK: cset   [[GT:w[0-9]+]], gt
 
 ; CHECK: bl      __unordtf2
 ; CHECK: cmp     w0, #0
-; CHECK: csinc   [[UNORDERED:w[0-9]+]], wzr, wzr, eq
+; CHECK: cset   [[UNORDERED:w[0-9]+]], ne
 ; CHECK: orr     w0, [[UNORDERED]], [[GT]]
 
   ret i1 %val
@@ -173,11 +173,11 @@ define i32 @test_br_cc() {
   %cond = fcmp olt fp128 %lhs, %rhs
 ; CHECK: bl      __getf2
 ; CHECK: cmp     w0, #0
-; CHECK: csinc   [[OGE:w[0-9]+]], wzr, wzr, lt
+; CHECK: cset   [[OGE:w[0-9]+]], ge
 
 ; CHECK: bl      __unordtf2
 ; CHECK: cmp     w0, #0
-; CHECK: csinc   [[UNORDERED:w[0-9]+]], wzr, wzr, eq
+; CHECK: cset   [[UNORDERED:w[0-9]+]], ne
 
 ; CHECK: orr     [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]]
 ; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]]
@@ -186,13 +186,13 @@ define i32 @test_br_cc() {
 iftrue:
   ret i32 42
 ; CHECK-NEXT: BB#
-; CHECK-NEXT: movz w0, #42
+; CHECK-NEXT: movz w0, #0x2a
 ; CHECK-NEXT: b [[REALRET:.LBB[0-9]+_[0-9]+]]
 
 iffalse:
   ret i32 29
 ; CHECK: [[RET29]]:
-; CHECK-NEXT: movz w0, #29
+; CHECK-NEXT: movz w0, #0x1d
 ; CHECK-NEXT: [[REALRET]]:
 ; CHECK: ret
 }
@@ -202,11 +202,10 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
 
   %val = select i1 %cond, fp128 %lhs, fp128 %rhs
   store fp128 %val, fp128* @lhs, align 16
-; CHECK: and [[BIT:w[0-9]+]], w0, #0x1
-; CHECK: cmp [[BIT]], #0
+; CHECK: tst w0, #0x1
 ; CHECK-NEXT: b.eq [[IFFALSE:.LBB[0-9]+_[0-9]+]]
 ; CHECK-NEXT: BB#
-; CHECK-NEXT: orr v[[VAL:[0-9]+]].16b, v0.16b, v0.16b
+; CHECK-NEXT: mov v[[VAL:[0-9]+]].16b, v0.16b
 ; CHECK-NEXT: [[IFFALSE]]:
 ; CHECK: str q[[VAL]], [{{x[0-9]+}}, :lo12:lhs]
   ret void
@@ -265,7 +264,7 @@ define fp128 @test_neg(fp128 %in) {
   ; Could in principle be optimized to fneg which we can't select, this makes
   ; sure that doesn't happen.
   %ret = fsub fp128 0xL00000000000000008000000000000000, %in
-; CHECK: orr v1.16b, v0.16b, v0.16b
+; CHECK: mov v1.16b, v0.16b
 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:[[MINUS0]]]
 ; CHECK: bl __subtf3