; Make sure that ARM backend with NEON handles vselect.
define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) {
-; CHECK: vcgt.s32 [[QR:q[0-9]+]], [[Q1:q[0-9]+]], [[Q2:q[0-9]+]]
-; CHECK: vbsl [[QR]], [[Q1]], [[Q2]]
+; CHECK: vmax.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
%cmpres = icmp sgt <4 x i32> %a, %b
%maxres = select <4 x i1> %cmpres, <4 x i32> %a, <4 x i32> %b
store <4 x i32> %maxres, <4 x i32>* %m
ret void
}
-; We adjusted the cost model of the following selects. When we improve code
-; lowering we also need to adjust the cost.
%T0_10 = type <16 x i16>
%T1_10 = type <16 x i1>
; CHECK-LABEL: func_blend10:
%v0 = load %T0_10, %T0_10* %loadaddr
%v1 = load %T0_10, %T0_10* %loadaddr2
%c = icmp slt %T0_10 %v0, %v1
-; CHECK: vbsl
-; CHECK: vbsl
+; CHECK: vmin.s16
+; CHECK: vmin.s16
; COST: func_blend10
-; COST: cost of 40 {{.*}} select
+; COST: cost of 2 {{.*}} select
%r = select %T1_10 %c, %T0_10 %v0, %T0_10 %v1
store %T0_10 %r, %T0_10* %storeaddr
ret void
%v0 = load %T0_14, %T0_14* %loadaddr
%v1 = load %T0_14, %T0_14* %loadaddr2
%c = icmp slt %T0_14 %v0, %v1
-; CHECK: vbsl
-; CHECK: vbsl
+; CHECK: vmin.s32
+; CHECK: vmin.s32
; COST: func_blend14
-; COST: cost of 41 {{.*}} select
+; COST: cost of 2 {{.*}} select
%r = select %T1_14 %c, %T0_14 %v0, %T0_14 %v1
store %T0_14 %r, %T0_14* %storeaddr
ret void
; CHECK-LABEL: func_blend15:
define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
%T1_15* %blend, %T0_15* %storeaddr) {
-; CHECK: vbsl
-; CHECK: vbsl
+; CHECK: vmin.s32
+; CHECK: vmin.s32
%v0 = load %T0_15, %T0_15* %loadaddr
%v1 = load %T0_15, %T0_15* %loadaddr2
%c = icmp slt %T0_15 %v0, %v1
; COST: func_blend15
-; COST: cost of 82 {{.*}} select
+; COST: cost of 4 {{.*}} select
%r = select %T1_15 %c, %T0_15 %v0, %T0_15 %v1
store %T0_15 %r, %T0_15* %storeaddr
ret void
}
+
+; We adjusted the cost model of the following selects. When we improve code
+; lowering we also need to adjust the cost.
%T0_18 = type <4 x i64>
%T1_18 = type <4 x i1>
; CHECK-LABEL: func_blend18: