[ARM] Use symbolic register names in .cfi directives only with IAS (PR19110)

[oota-llvm.git] / test / CodeGen / ARM / vrev.ll

diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll
index 0f0ea2b93220502a73cd73aea4c27aad7675593e..b6da694e18052fcbefbd709909706c01a477fd7e 100644 (file)
--- a/test/CodeGen/ARM/vrev.ll
+++ b/test/CodeGen/ARM/vrev.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev64D8:
+;CHECK-LABEL: test_vrev64D8:
 ;CHECK: vrev64.8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -9,7 +9,7 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
-;CHECK: test_vrev64D16:
+;CHECK-LABEL: test_vrev64D16:
 ;CHECK: vrev64.16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
@@ -17,7 +17,7 @@ define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
-;CHECK: test_vrev64D32:
+;CHECK-LABEL: test_vrev64D32:
 ;CHECK: vrev64.32
        %tmp1 = load <2 x i32>* %A
        %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
@@ -25,7 +25,7 @@ define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
-;CHECK: test_vrev64Df:
+;CHECK-LABEL: test_vrev64Df:
 ;CHECK: vrev64.32
        %tmp1 = load <2 x float>* %A
        %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
@@ -33,7 +33,7 @@ define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
 }
 
 define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev64Q8:
+;CHECK-LABEL: test_vrev64Q8:
 ;CHECK: vrev64.8
        %tmp1 = load <16 x i8>* %A
        %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
@@ -41,7 +41,7 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev64Q16:
+;CHECK-LABEL: test_vrev64Q16:
 ;CHECK: vrev64.16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
@@ -49,7 +49,7 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
-;CHECK: test_vrev64Q32:
+;CHECK-LABEL: test_vrev64Q32:
 ;CHECK: vrev64.32
        %tmp1 = load <4 x i32>* %A
        %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
@@ -57,7 +57,7 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
-;CHECK: test_vrev64Qf:
+;CHECK-LABEL: test_vrev64Qf:
 ;CHECK: vrev64.32
        %tmp1 = load <4 x float>* %A
        %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
@@ -65,7 +65,7 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
 }
 
 define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev32D8:
+;CHECK-LABEL: test_vrev32D8:
 ;CHECK: vrev32.8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
@@ -73,7 +73,7 @@ define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
-;CHECK: test_vrev32D16:
+;CHECK-LABEL: test_vrev32D16:
 ;CHECK: vrev32.16
        %tmp1 = load <4 x i16>* %A
        %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
@@ -81,7 +81,7 @@ define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
 }
 
 define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev32Q8:
+;CHECK-LABEL: test_vrev32Q8:
 ;CHECK: vrev32.8
        %tmp1 = load <16 x i8>* %A
        %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
@@ -89,7 +89,7 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev32Q16:
+;CHECK-LABEL: test_vrev32Q16:
 ;CHECK: vrev32.16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
@@ -97,7 +97,7 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
 }
 
 define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev16D8:
+;CHECK-LABEL: test_vrev16D8:
 ;CHECK: vrev16.8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
@@ -105,7 +105,7 @@ define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
 }
 
 define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev16Q8:
+;CHECK-LABEL: test_vrev16Q8:
 ;CHECK: vrev16.8
        %tmp1 = load <16 x i8>* %A
        %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
@@ -115,7 +115,7 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
 ; Undef shuffle indices should not prevent matching to VREV:
 
 define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev64D8_undef:
+;CHECK-LABEL: test_vrev64D8_undef:
 ;CHECK: vrev64.8
        %tmp1 = load <8 x i8>* %A
        %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -123,7 +123,7 @@ define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev32Q16_undef:
+;CHECK-LABEL: test_vrev32Q16_undef:
 ;CHECK: vrev32.16
        %tmp1 = load <8 x i16>* %A
        %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
@@ -133,7 +133,7 @@ define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
 ; A vcombine feeding a VREV should not obscure things.  Radar 8597007.
 
 define void @test_with_vcombine(<4 x float>* %v) nounwind {
-;CHECK: test_with_vcombine:
+;CHECK-LABEL: test_with_vcombine:
 ;CHECK-NOT: vext
 ;CHECK: vrev64.32
   %tmp1 = load <4 x float>* %v, align 16
@@ -148,11 +148,11 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind {
   ret void
 }
 
-; vrev <4 x i16> should use VREV32 and not VREV64
+; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
+; to <2 x i16> when stored to memory.
 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
-; CHECK: test_vrev64:
-; CHECK: vext.16
-; CHECK: vrev32.16
+; CHECK-LABEL: test_vrev64:
+; CHECK: vst1.32
 entry:
   %0 = bitcast <4 x i16>* %source to <8 x i16>*
   %tmp2 = load <8 x i16>* %0, align 4
@@ -163,3 +163,18 @@ entry:
   store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
   ret void
 }
+
+; Test vrev of float4
+define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp {
+; CHECK: float_vrev64
+; CHECK: vext.32
+; CHECK: vrev64.32
+entry:
+  %0 = bitcast float* %source to <4 x float>*
+  %tmp2 = load <4 x float>* %0, align 4
+  %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
+  %arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11
+  store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
+  ret void
+}
+