[ARM] When a bitcast is about to be turned into a VMOVDRR, try to combine it

[oota-llvm.git] / test / CodeGen / ARM / vqshrn.ll

diff --git a/test/CodeGen/ARM/vqshrn.ll b/test/CodeGen/ARM/vqshrn.ll
index 4abae700f8770e1d8c938be8128369f60e4fcff4..b4b5e96d4579b428b255488b7b414e55654ef339 100644 (file)
--- a/test/CodeGen/ARM/vqshrn.ll
+++ b/test/CodeGen/ARM/vqshrn.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
 
 define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshrns8:
 ;CHECK: vqshrn.s16
-       %tmp1 = load <8 x i16>* %A
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
        ret <8 x i8> %tmp2
 }
@@ -11,7 +11,7 @@ define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshrns16:
 ;CHECK: vqshrn.s32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
        ret <4 x i16> %tmp2
 }
@@ -19,7 +19,7 @@ define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshrns32:
 ;CHECK: vqshrn.s64
-       %tmp1 = load <2 x i64>* %A
+       %tmp1 = load <2 x i64>, <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
        ret <2 x i32> %tmp2
 }
@@ -27,7 +27,7 @@ define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshrnu8:
 ;CHECK: vqshrn.u16
-       %tmp1 = load <8 x i16>* %A
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
        ret <8 x i8> %tmp2
 }
@@ -35,7 +35,7 @@ define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshrnu16:
 ;CHECK: vqshrn.u32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
        ret <4 x i16> %tmp2
 }
@@ -43,7 +43,7 @@ define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshrnu32:
 ;CHECK: vqshrn.u64
-       %tmp1 = load <2 x i64>* %A
+       %tmp1 = load <2 x i64>, <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
        ret <2 x i32> %tmp2
 }
@@ -51,7 +51,7 @@ define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqshruns8:
 ;CHECK: vqshrun.s16
-       %tmp1 = load <8 x i16>* %A
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
        ret <8 x i8> %tmp2
 }
@@ -59,7 +59,7 @@ define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqshruns16:
 ;CHECK: vqshrun.s32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
        ret <4 x i16> %tmp2
 }
@@ -67,7 +67,7 @@ define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqshruns32:
 ;CHECK: vqshrun.s64
-       %tmp1 = load <2 x i64>* %A
+       %tmp1 = load <2 x i64>, <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
        ret <2 x i32> %tmp2
 }
@@ -87,7 +87,7 @@ declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind
 define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqrshrns8:
 ;CHECK: vqrshrn.s16
-       %tmp1 = load <8 x i16>* %A
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
        ret <8 x i8> %tmp2
 }
@@ -95,7 +95,7 @@ define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqrshrns16:
 ;CHECK: vqrshrn.s32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
        ret <4 x i16> %tmp2
 }
@@ -103,7 +103,7 @@ define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqrshrns32:
 ;CHECK: vqrshrn.s64
-       %tmp1 = load <2 x i64>* %A
+       %tmp1 = load <2 x i64>, <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
        ret <2 x i32> %tmp2
 }
@@ -111,7 +111,7 @@ define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqrshrnu8:
 ;CHECK: vqrshrn.u16
-       %tmp1 = load <8 x i16>* %A
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
        ret <8 x i8> %tmp2
 }
@@ -119,7 +119,7 @@ define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqrshrnu16:
 ;CHECK: vqrshrn.u32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
        ret <4 x i16> %tmp2
 }
@@ -127,7 +127,7 @@ define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqrshrnu32:
 ;CHECK: vqrshrn.u64
-       %tmp1 = load <2 x i64>* %A
+       %tmp1 = load <2 x i64>, <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
        ret <2 x i32> %tmp2
 }
@@ -135,7 +135,7 @@ define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
 define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
 ;CHECK-LABEL: vqrshruns8:
 ;CHECK: vqrshrun.s16
-       %tmp1 = load <8 x i16>* %A
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
        ret <8 x i8> %tmp2
 }
@@ -143,7 +143,7 @@ define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
 define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vqrshruns16:
 ;CHECK: vqrshrun.s32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
        ret <4 x i16> %tmp2
 }
@@ -151,7 +151,7 @@ define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
 define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
 ;CHECK-LABEL: vqrshruns32:
 ;CHECK: vqrshrun.s64
-       %tmp1 = load <2 x i64>* %A
+       %tmp1 = load <2 x i64>, <2 x i64>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
        ret <2 x i32> %tmp2
 }