Add float patterns for Neon vld1-lane/dup and vst1-lane operations.

[oota-llvm.git] / test / CodeGen / ARM / vlddup.ll

diff --git a/test/CodeGen/ARM/vlddup.ll b/test/CodeGen/ARM/vlddup.ll
index bb07ce2d2398ca54f6043a6a7ecd0298b697055a..033febbb24adfd1ef6ee73d43c3cd5f8714f5c5b 100644 (file)
--- a/test/CodeGen/ARM/vlddup.ll
+++ b/test/CodeGen/ARM/vlddup.ll
@@ -30,6 +30,15 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind {
         ret <2 x i32> %tmp3
 }
 
+define <2 x float> @vld1dupf(float* %A) nounwind {
+;CHECK: vld1dupf:
+;CHECK: vld1.32 {d16[]}, [r0]
+       %tmp0 = load float* %A
+        %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
+        %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
+        ret <2 x float> %tmp2
+}
+
 define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
 ;CHECK: vld1dupQi8:
 ;Check the (default) alignment value.
@@ -40,6 +49,15 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
         ret <16 x i8> %tmp3
 }
 
+define <4 x float> @vld1dupQf(float* %A) nounwind {
+;CHECK: vld1dupQf:
+;CHECK: vld1.32 {d16[], d17[]}, [r0]
+        %tmp0 = load float* %A
+        %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
+        %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
+        ret <4 x float> %tmp2
+}
+
 %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
 %struct.__neon_int4x16x2_t = type { <4 x i16>, <4 x i16> }
 %struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> }