[ARM]: Extend -mfpu options for half-precision and vfpv3xd

[oota-llvm.git] / test / CodeGen / ARM / vld4.ll

diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll
index e244e4b074ce17983792bb0d8a2df4a3d9d55b23..575e0fa717fb3c306babab271342e201c90d4879 100644 (file)
--- a/test/CodeGen/ARM/vld4.ll
+++ b/test/CodeGen/ARM/vld4.ll
@@ -26,7 +26,7 @@ define <8 x i8> @vld4i8(i8* %A) nounwind {
 define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
 ;CHECK-LABEL: vld4i8_update:
 ;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1
-       %A = load i8** %ptr
+       %A = load i8*, i8** %ptr
        %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
        %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
        %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
@@ -126,7 +126,7 @@ define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
 ;CHECK-LABEL: vld4Qi16_update:
 ;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]!
 ;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]!
-       %A = load i16** %ptr
+       %A = load i16*, i16** %ptr
        %tmp0 = bitcast i16* %A to i8*
        %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8)
        %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0