[X86][SSE] Added tests for i8/i16 vector shifts

[oota-llvm.git] / test / CodeGen / ARM / vdiv_combine.ll

diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll
index 3b43be46b4520922055052cfa0105217a019da68..8c6e4ba350549a6b97c3db1f9d76a717e830dd9f 100644 (file)
--- a/test/CodeGen/ARM/vdiv_combine.ll
+++ b/test/CodeGen/ARM/vdiv_combine.ll
@@ -11,7 +11,7 @@ declare void @foo_int32x4_t(<4 x i32>)
 ; CHECK-NOT: {{vdiv|vmul}}
 define void @t1() nounwind {
 entry:
-  %tmp = load i32* @iin, align 4
+  %tmp = load i32, i32* @iin, align 4
   %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
   %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -27,7 +27,7 @@ declare void @foo_float32x2_t(<2 x float>)
 ; CHECK-NOT: {{vdiv|vmul}}
 define void @t2() nounwind {
 entry:
-  %tmp = load i32* @uin, align 4
+  %tmp = load i32, i32* @uin, align 4
   %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
   %vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -41,7 +41,7 @@ entry:
 ; CHECK: {{vdiv|vmul}}
 define void @t3() nounwind {
 entry:
-  %tmp = load i32* @iin, align 4
+  %tmp = load i32, i32* @iin, align 4
   %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
   %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -55,7 +55,7 @@ entry:
 ; CHECK: {{vdiv|vmul}}
 define void @t4() nounwind {
 entry:
-  %tmp = load i32* @iin, align 4
+  %tmp = load i32, i32* @iin, align 4
   %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
   %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -69,7 +69,7 @@ entry:
 ; CHECK-NOT: {{vdiv|vmul}}
 define void @t5() nounwind {
 entry:
-  %tmp = load i32* @iin, align 4
+  %tmp = load i32, i32* @iin, align 4
   %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
   %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
@@ -83,7 +83,7 @@ entry:
 ; CHECK-NOT: {{vdiv|vmul}}
 define void @t6() nounwind {
 entry:
-  %tmp = load i32* @iin, align 4
+  %tmp = load i32, i32* @iin, align 4
   %vecinit.i = insertelement <4 x i32> undef, i32 %tmp, i32 0
   %vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %tmp, i32 1
   %vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %tmp, i32 2
@@ -97,7 +97,7 @@ entry:
 declare void @foo_float32x4_t(<4 x float>)
 
 define <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) {
-; CHECK: fix_unsigned_i16_to_float:
+; CHECK-LABEL: fix_unsigned_i16_to_float:
 ; CHECK: vmovl.u16 [[TMP:q[0-9]+]], {{d[0-9]+}}
 ; CHECK: vcvt.f32.u32 {{q[0-9]+}}, [[TMP]], #1
 
@@ -107,7 +107,7 @@ define <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) {
 }
 
 define <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) {
-; CHECK: fix_signed_i16_to_float:
+; CHECK-LABEL: fix_signed_i16_to_float:
 ; CHECK: vmovl.s16 [[TMP:q[0-9]+]], {{d[0-9]+}}
 ; CHECK: vcvt.f32.s32 {{q[0-9]+}}, [[TMP]], #1
 
@@ -117,7 +117,7 @@ define <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) {
 }
 
 define <2 x float> @fix_i64_to_float(<2 x i64> %in) {
-; CHECK: fix_i64_to_float:
+; CHECK-LABEL: fix_i64_to_float:
 ; CHECK: bl
 ; CHECK: bl
 
@@ -127,7 +127,7 @@ define <2 x float> @fix_i64_to_float(<2 x i64> %in) {
 }
 
 define <2 x double> @fix_i64_to_double(<2 x i64> %in) {
-; CHECK: fix_i64_to_double:
+; CHECK-LABEL: fix_i64_to_double:
 ; CHECK: bl
 ; CHECK: bl