[ARM] When a bitcast is about to be turned into a VMOVDRR, try to combine it

[oota-llvm.git] / test / CodeGen / ARM / vcvt.ll

diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll
index 4f17dc5594808959172788903854912c7bf0220c..78105f7e0ad10de170057cdf1b69d49835eb010a 100644 (file)
--- a/test/CodeGen/ARM/vcvt.ll
+++ b/test/CodeGen/ARM/vcvt.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+neon,+fp16 %s -o - | FileCheck %s
 
 define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvt_f32tos32:
 ;CHECK: vcvt.s32.f32
-       %tmp1 = load <2 x float>* %A
+       %tmp1 = load <2 x float>, <2 x float>* %A
        %tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
        ret <2 x i32> %tmp2
 }
@@ -11,7 +11,7 @@ define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
 define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvt_f32tou32:
 ;CHECK: vcvt.u32.f32
-       %tmp1 = load <2 x float>* %A
+       %tmp1 = load <2 x float>, <2 x float>* %A
        %tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
        ret <2 x i32> %tmp2
 }
@@ -19,7 +19,7 @@ define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
 define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvt_s32tof32:
 ;CHECK: vcvt.f32.s32
-       %tmp1 = load <2 x i32>* %A
+       %tmp1 = load <2 x i32>, <2 x i32>* %A
        %tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
        ret <2 x float> %tmp2
 }
@@ -27,7 +27,7 @@ define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
 define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvt_u32tof32:
 ;CHECK: vcvt.f32.u32
-       %tmp1 = load <2 x i32>* %A
+       %tmp1 = load <2 x i32>, <2 x i32>* %A
        %tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
        ret <2 x float> %tmp2
 }
@@ -35,7 +35,7 @@ define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
 define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_f32tos32:
 ;CHECK: vcvt.s32.f32
-       %tmp1 = load <4 x float>* %A
+       %tmp1 = load <4 x float>, <4 x float>* %A
        %tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
        ret <4 x i32> %tmp2
 }
@@ -43,7 +43,7 @@ define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
 define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_f32tou32:
 ;CHECK: vcvt.u32.f32
-       %tmp1 = load <4 x float>* %A
+       %tmp1 = load <4 x float>, <4 x float>* %A
        %tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
        ret <4 x i32> %tmp2
 }
@@ -51,7 +51,7 @@ define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
 define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_s32tof32:
 ;CHECK: vcvt.f32.s32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
        ret <4 x float> %tmp2
 }
@@ -59,7 +59,7 @@ define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
 define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_u32tof32:
 ;CHECK: vcvt.f32.u32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
        ret <4 x float> %tmp2
 }
@@ -67,7 +67,7 @@ define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
 define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvt_n_f32tos32:
 ;CHECK: vcvt.s32.f32
-       %tmp1 = load <2 x float>* %A
+       %tmp1 = load <2 x float>, <2 x float>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
        ret <2 x i32> %tmp2
 }
@@ -75,7 +75,7 @@ define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
 define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvt_n_f32tou32:
 ;CHECK: vcvt.u32.f32
-       %tmp1 = load <2 x float>* %A
+       %tmp1 = load <2 x float>, <2 x float>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
        ret <2 x i32> %tmp2
 }
@@ -83,7 +83,7 @@ define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
 define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvt_n_s32tof32:
 ;CHECK: vcvt.f32.s32
-       %tmp1 = load <2 x i32>* %A
+       %tmp1 = load <2 x i32>, <2 x i32>* %A
        %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
        ret <2 x float> %tmp2
 }
@@ -91,7 +91,7 @@ define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
 define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvt_n_u32tof32:
 ;CHECK: vcvt.f32.u32
-       %tmp1 = load <2 x i32>* %A
+       %tmp1 = load <2 x i32>, <2 x i32>* %A
        %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
        ret <2 x float> %tmp2
 }
@@ -104,7 +104,7 @@ declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwi
 define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_n_f32tos32:
 ;CHECK: vcvt.s32.f32
-       %tmp1 = load <4 x float>* %A
+       %tmp1 = load <4 x float>, <4 x float>* %A
        %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
        ret <4 x i32> %tmp2
 }
@@ -112,7 +112,7 @@ define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
 define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_n_f32tou32:
 ;CHECK: vcvt.u32.f32
-       %tmp1 = load <4 x float>* %A
+       %tmp1 = load <4 x float>, <4 x float>* %A
        %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
        ret <4 x i32> %tmp2
 }
@@ -120,7 +120,7 @@ define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
 define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_n_s32tof32:
 ;CHECK: vcvt.f32.s32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
        ret <4 x float> %tmp2
 }
@@ -128,7 +128,7 @@ define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
 define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
 ;CHECK-LABEL: vcvtQ_n_u32tof32:
 ;CHECK: vcvt.f32.u32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
        ret <4 x float> %tmp2
 }
@@ -141,7 +141,7 @@ declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwi
 define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: vcvt_f16tof32:
 ;CHECK: vcvt.f32.f16
-       %tmp1 = load <4 x i16>* %A
+       %tmp1 = load <4 x i16>, <4 x i16>* %A
        %tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1)
        ret <4 x float> %tmp2
 }
@@ -149,7 +149,7 @@ define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
 define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
 ;CHECK-LABEL: vcvt_f32tof16:
 ;CHECK: vcvt.f16.f32
-       %tmp1 = load <4 x float>* %A
+       %tmp1 = load <4 x float>, <4 x float>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1)
        ret <4 x i16> %tmp2
 }
@@ -180,8 +180,8 @@ define <2 x i64> @fix_float_to_i64(<2 x float> %in) {
 
 define <4 x i16> @fix_double_to_i16(<4 x double> %in) {
 ; CHECK-LABEL: fix_double_to_i16:
-; CHECK: vcvt.s32.f64
-; CHECK: vcvt.s32.f64
+; CHECK: vcvt.u32.f64
+; CHECK: vcvt.u32.f64
 
   %scale = fmul <4 x double> %in, <double 2.0, double 2.0, double 2.0, double 2.0>
   %conv = fptoui <4 x double> %scale to <4 x i16>