ARM & AArch64: merge NEON absolute compare intrinsics

[oota-llvm.git] / test / CodeGen / ARM / vcgt.ll

diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll
index 056866fe994b39c2cfb3452994c234535a4cbf59..adee76a2fbb943355b7b2098a1ef0afc5fe87b68 100644 (file)
--- a/test/CodeGen/ARM/vcgt.ll
+++ b/test/CodeGen/ARM/vcgt.ll
@@ -146,7 +146,7 @@ define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 ;CHECK: vacgt.f32
        %tmp1 = load <2 x float>* %A
        %tmp2 = load <2 x float>* %B
-       %tmp3 = call <2 x i32> @llvm.arm.neon.vacgtd(<2 x float> %tmp1, <2 x float> %tmp2)
+       %tmp3 = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
        ret <2 x i32> %tmp3
 }
 
@@ -155,7 +155,7 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 ;CHECK: vacgt.f32
        %tmp1 = load <4 x float>* %A
        %tmp2 = load <4 x float>* %B
-       %tmp3 = call <4 x i32> @llvm.arm.neon.vacgtq(<4 x float> %tmp1, <4 x float> %tmp2)
+       %tmp3 = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
        ret <4 x i32> %tmp3
 }
 
@@ -172,8 +172,8 @@ define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
        ret <4 x i32> %tmp4
 }
 
-declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
 
 define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: vcgti8Z: