Move the complex address expression out of DIVariable and into an extra

[oota-llvm.git] / test / CodeGen / ARM / vbsl-constant.ll

diff --git a/test/CodeGen/ARM/vbsl-constant.ll b/test/CodeGen/ARM/vbsl-constant.ll
index 14e668efb1da4b29e95371e6ed884fd1e5a6bbe0..5e033fe2a64758fd79b5f20552bada8c34e25f34 100644 (file)
--- a/test/CodeGen/ARM/vbsl-constant.ll
+++ b/test/CodeGen/ARM/vbsl-constant.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s
 
 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: v_bsli8:
-;CHECK: vldr.64
-;CHECK: vldr.64
+;CHECK-LABEL: v_bsli8:
+;CHECK: vldr
+;CHECK: vldr
 ;CHECK: vbsl
        %tmp1 = load <8 x i8>* %A
        %tmp2 = load <8 x i8>* %B
@@ -15,9 +15,9 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: v_bsli16:
-;CHECK: vldr.64
-;CHECK: vldr.64
+;CHECK-LABEL: v_bsli16:
+;CHECK: vldr
+;CHECK: vldr
 ;CHECK: vbsl
        %tmp1 = load <4 x i16>* %A
        %tmp2 = load <4 x i16>* %B
@@ -29,9 +29,9 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: v_bsli32:
-;CHECK: vldr.64
-;CHECK: vldr.64
+;CHECK-LABEL: v_bsli32:
+;CHECK: vldr
+;CHECK: vldr
 ;CHECK: vbsl
        %tmp1 = load <2 x i32>* %A
        %tmp2 = load <2 x i32>* %B
@@ -43,10 +43,10 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
-;CHECK: v_bsli64:
-;CHECK: vldr.64
-;CHECK: vldr.64
-;CHECK: vldr.64
+;CHECK-LABEL: v_bsli64:
+;CHECK: vldr
+;CHECK: vldr
+;CHECK: vldr
 ;CHECK: vbsl
        %tmp1 = load <1 x i64>* %A
        %tmp2 = load <1 x i64>* %B
@@ -58,9 +58,9 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind
 }
 
 define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: v_bslQi8:
-;CHECK: vldmia
-;CHECK: vldmia
+;CHECK-LABEL: v_bslQi8:
+;CHECK: vld1.32
+;CHECK: vld1.32
 ;CHECK: vbsl
        %tmp1 = load <16 x i8>* %A
        %tmp2 = load <16 x i8>* %B
@@ -72,9 +72,9 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 }
 
 define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: v_bslQi16:
-;CHECK: vldmia
-;CHECK: vldmia
+;CHECK-LABEL: v_bslQi16:
+;CHECK: vld1.32
+;CHECK: vld1.32
 ;CHECK: vbsl
        %tmp1 = load <8 x i16>* %A
        %tmp2 = load <8 x i16>* %B
@@ -86,9 +86,9 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin
 }
 
 define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: v_bslQi32:
-;CHECK: vldmia
-;CHECK: vldmia
+;CHECK-LABEL: v_bslQi32:
+;CHECK: vld1.32
+;CHECK: vld1.32
 ;CHECK: vbsl
        %tmp1 = load <4 x i32>* %A
        %tmp2 = load <4 x i32>* %B
@@ -100,10 +100,10 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin
 }
 
 define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
-;CHECK: v_bslQi64:
-;CHECK: vldmia
-;CHECK: vldmia
-;CHECK: vldmia
+;CHECK-LABEL: v_bslQi64:
+;CHECK: vld1.32
+;CHECK: vld1.32
+;CHECK: vld1.64
 ;CHECK: vbsl
        %tmp1 = load <2 x i64>* %A
        %tmp2 = load <2 x i64>* %B