[ARM] Add instruction selection patterns for vmin/vmax

[oota-llvm.git] / test / CodeGen / ARM / vabs.ll

diff --git a/test/CodeGen/ARM/vabs.ll b/test/CodeGen/ARM/vabs.ll
index f1aafed6b6676cc32e1d4cd733b03ec77eab8a03..38c6d6c28aedfb87030b5fca2077b7683d6e428c 100644 (file)
--- a/test/CodeGen/ARM/vabs.ll
+++ b/test/CodeGen/ARM/vabs.ll
@@ -1,76 +1,131 @@
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
 
 define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
-;CHECK: vabss8:
+;CHECK-LABEL: vabss8:
 ;CHECK: vabs.s8
-       %tmp1 = load <8 x i8>* %A
+       %tmp1 = load <8 x i8>, <8 x i8>* %A
        %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
        ret <8 x i8> %tmp2
 }
 
 define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
-;CHECK: vabss16:
+;CHECK-LABEL: vabss16:
 ;CHECK: vabs.s16
-       %tmp1 = load <4 x i16>* %A
+       %tmp1 = load <4 x i16>, <4 x i16>* %A
        %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
        ret <4 x i16> %tmp2
 }
 
 define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
-;CHECK: vabss32:
+;CHECK-LABEL: vabss32:
 ;CHECK: vabs.s32
-       %tmp1 = load <2 x i32>* %A
+       %tmp1 = load <2 x i32>, <2 x i32>* %A
        %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
        ret <2 x i32> %tmp2
 }
 
 define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
-;CHECK: vabsf32:
+;CHECK-LABEL: vabsf32:
 ;CHECK: vabs.f32
-       %tmp1 = load <2 x float>* %A
-       %tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1)
+       %tmp1 = load <2 x float>, <2 x float>* %A
+       %tmp2 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %tmp1)
        ret <2 x float> %tmp2
 }
 
 define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vabsQs8:
+;CHECK-LABEL: vabsQs8:
 ;CHECK: vabs.s8
-       %tmp1 = load <16 x i8>* %A
+       %tmp1 = load <16 x i8>, <16 x i8>* %A
        %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
        ret <16 x i8> %tmp2
 }
 
 define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vabsQs16:
+;CHECK-LABEL: vabsQs16:
 ;CHECK: vabs.s16
-       %tmp1 = load <8 x i16>* %A
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
        %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
        ret <8 x i16> %tmp2
 }
 
 define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vabsQs32:
+;CHECK-LABEL: vabsQs32:
 ;CHECK: vabs.s32
-       %tmp1 = load <4 x i32>* %A
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
        %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
        ret <4 x i32> %tmp2
 }
 
 define <4 x float> @vabsQf32(<4 x float>* %A) nounwind {
-;CHECK: vabsQf32:
+;CHECK-LABEL: vabsQf32:
 ;CHECK: vabs.f32
-       %tmp1 = load <4 x float>* %A
-       %tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
+       %tmp1 = load <4 x float>, <4 x float>* %A
+       %tmp2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %tmp1)
        ret <4 x float> %tmp2
 }
 
 declare <8 x i8>  @llvm.arm.neon.vabs.v8i8(<8 x i8>) nounwind readnone
 declare <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16>) nounwind readnone
 declare <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32>) nounwind readnone
-declare <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float>) nounwind readnone
+declare <2 x float> @llvm.fabs.v2f32(<2 x float>) nounwind readnone
 
 declare <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8>) nounwind readnone
 declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone
 declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone
-declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone
 
+define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
+;CHECK-LABEL: vqabss8:
+;CHECK: vqabs.s8
+       %tmp1 = load <8 x i8>, <8 x i8>* %A
+       %tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
+       ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
+;CHECK-LABEL: vqabss16:
+;CHECK: vqabs.s16
+       %tmp1 = load <4 x i16>, <4 x i16>* %A
+       %tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
+       ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
+;CHECK-LABEL: vqabss32:
+;CHECK: vqabs.s32
+       %tmp1 = load <2 x i32>, <2 x i32>* %A
+       %tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
+       ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
+;CHECK-LABEL: vqabsQs8:
+;CHECK: vqabs.s8
+       %tmp1 = load <16 x i8>, <16 x i8>* %A
+       %tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
+       ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: vqabsQs16:
+;CHECK: vqabs.s16
+       %tmp1 = load <8 x i16>, <8 x i16>* %A
+       %tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
+       ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: vqabsQs32:
+;CHECK: vqabs.s32
+       %tmp1 = load <4 x i32>, <4 x i32>* %A
+       %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
+       ret <4 x i32> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vqabs.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) nounwind readnone