Change ARM scheduling default to list-hybrid if the target supports floating point...

[oota-llvm.git] / test / CodeGen / ARM / reg_sequence.ll

diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll
index 1a27d4d93979adb5948aa8a922d55b7a99e24e2b..3ba82ccdfa96e3056a7c6b4b36625ebd1aa77fa2 100644 (file)
--- a/test/CodeGen/ARM/reg_sequence.ll
+++ b/test/CodeGen/ARM/reg_sequence.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
 ; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's.
 
 %struct.int16x8_t = type { <8 x i16> }
@@ -45,12 +45,12 @@ define arm_apcscc void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocaptur
 entry:
 ; CHECK:        t2:
 ; CHECK:        vld1.16
-; CHECK-NOT:    vmov
-; CHECK:        vmul.i16
 ; CHECK:        vld1.16
-; CHECK:        vst1.16
 ; CHECK-NOT:    vmov
 ; CHECK:        vmul.i16
+; CHECK:        vmul.i16
+; CHECK-NOT:    vmov
+; CHECK:        vst1.16
 ; CHECK:        vst1.16
   %0 = getelementptr inbounds %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1]
   %1 = load <8 x i16>* %0, align 16               ; <<8 x i16>> [#uses=1]
@@ -238,8 +238,8 @@ bb14:                                             ; preds = %bb6
 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
 ; CHECK:        t9:
 ; CHECK:        vldr.64
-; CHECK-NEXT:   vstmia r0, {d0,d1}
-; CHECK-NEXT:   vmov.i8 d1
+; CHECK:        vmov.i8 d1
+; CHECK-NEXT:   vstmia r0, {d2,d3}
 ; CHECK-NEXT:   vstmia r0, {d0,d1}
   %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2]
   %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]